13 #define IMX208_REG_MODE_SELECT		0x0100
14 #define IMX208_MODE_STANDBY		0x00
15 #define IMX208_MODE_STREAMING		0x01
18 #define IMX208_REG_CHIP_ID		0x0000
19 #define IMX208_CHIP_ID			0x0208
22 #define IMX208_REG_VTS			0x0340
23 #define IMX208_VTS_60FPS		0x0472
24 #define IMX208_VTS_BINNING		0x0239
25 #define IMX208_VTS_60FPS_MIN		0x0458
26 #define IMX208_VTS_BINNING_MIN		0x0230
27 #define IMX208_VTS_MAX			0xffff
34 #define IMX208_REG_EXPOSURE		0x0202
37 #define IMX208_EXPOSURE_DEFAULT		0x190
41 #define IMX208_REG_ANALOG_GAIN		0x0204
42 #define IMX208_ANA_GAIN_MIN		0
43 #define IMX208_ANA_GAIN_MAX		0x00e0
45 #define IMX208_ANA_GAIN_DEFAULT		0x0
48 #define IMX208_REG_GR_DIGITAL_GAIN	0x020e
49 #define IMX208_REG_R_DIGITAL_GAIN	0x0210
50 #define IMX208_REG_B_DIGITAL_GAIN	0x0212
51 #define IMX208_REG_GB_DIGITAL_GAIN	0x0214
55 #define IMX208_REG_ORIENTATION_CONTROL	0x0101
58 #define IMX208_REG_TEST_PATTERN_MODE	0x0600
59 #define IMX208_TEST_PATTERN_DISABLE	0x0
60 #define IMX208_TEST_PATTERN_SOLID_COLOR	0x1
61 #define IMX208_TEST_PATTERN_COLOR_BARS	0x2
62 #define IMX208_TEST_PATTERN_GREY_COLOR	0x3
63 #define IMX208_TEST_PATTERN_PN9		0x4
64 #define IMX208_TEST_PATTERN_FIX_1	0x100
65 #define IMX208_TEST_PATTERN_FIX_2	0x101
66 #define IMX208_TEST_PATTERN_FIX_3	0x102
67 #define IMX208_TEST_PATTERN_FIX_4	0x103
68 #define IMX208_TEST_PATTERN_FIX_5	0x104
69 #define IMX208_TEST_PATTERN_FIX_6	0x105
72 #define IMX208_OTP_BASE			0x3500
111 	{0x0305, 0x02},
112 	{0x0307, 0x50},
113 	{0x303C, 0x3C},
117 	{0x0340, 0x04},
118 	{0x0341, 0x72},
119 	{0x0342, 0x04},
120 	{0x0343, 0x64},
121 	{0x034C, 0x07},
122 	{0x034D, 0x90},
123 	{0x034E, 0x04},
124 	{0x034F, 0x48},
125 	{0x0381, 0x01},
126 	{0x0383, 0x01},
127 	{0x0385, 0x01},
128 	{0x0387, 0x01},
129 	{0x3048, 0x00},
130 	{0x3050, 0x01},
131 	{0x30D5, 0x00},
132 	{0x3301, 0x00},
133 	{0x3318, 0x62},
134 	{0x0202, 0x01},
135 	{0x0203, 0x90},
136 	{0x0205, 0x00},
140 	{0x0340, 0x02},
141 	{0x0341, 0x39},
142 	{0x0342, 0x08},
143 	{0x0343, 0xC8},
144 	{0x034C, 0x03},
145 	{0x034D, 0xC8},
146 	{0x034E, 0x02},
147 	{0x034F, 0x24},
148 	{0x0381, 0x01},
149 	{0x0383, 0x03},
150 	{0x0385, 0x01},
151 	{0x0387, 0x03},
152 	{0x3048, 0x01},
153 	{0x3050, 0x02},
154 	{0x30D5, 0x03},
155 	{0x3301, 0x10},
156 	{0x3318, 0x75},
157 	{0x0202, 0x01},
158 	{0x0203, 0x90},
159 	{0x0205, 0x00},
326 	u8 addr_buf[2] = { reg >> 8, reg & 0xff };  in imx208_read_reg()
327 	u8 data_buf[4] = { 0, };  in imx208_read_reg()
334 	msgs[0].addr = client->addr;  in imx208_read_reg()
335 	msgs[0].flags = 0;  in imx208_read_reg()
336 	msgs[0].len = ARRAY_SIZE(addr_buf);  in imx208_read_reg()
337 	msgs[0].buf = addr_buf;  in imx208_read_reg()
351 	return 0;  in imx208_read_reg()
368 	return 0;  in imx208_write_reg()
379 	for (i = 0; i < len; i++) {  in imx208_write_regs()
384 					    "Failed to write reg 0x%4.4x. error = %d\n",  in imx208_write_regs()
391 	return 0;  in imx208_write_regs()
398 		v4l2_subdev_state_get_format(fh->state, 0);  in imx208_open()
401 	try_fmt->width = supported_modes[0].width;  in imx208_open()
402 	try_fmt->height = supported_modes[0].height;  in imx208_open()
406 	return 0;  in imx208_open()
442 		return 0;  in imx208_set_ctrl()
475 			"ctrl(id:0x%x,val:0x%x) is not handled\n",  in imx208_set_ctrl()
494 	.min = 0,
496 	.step = 0,
497 	.def = 0,
498 	.menu_skip_mask = 0,
508 	if (code->index > 0)  in imx208_enum_mbus_code()
513 	return 0;  in imx208_enum_mbus_code()
533 	return 0;  in imx208_enum_frame_size()
556 	return 0;  in __imx208_get_pad_format()
618 	return 0;  in imx208_set_pad_format()
628 		return 0;  in imx208_identify_module()
646 	return 0;  in imx208_identify_module()
703 	return 0;  in imx208_stop_streaming()
710 	int ret = 0;  in imx208_set_stream()
773 	u8 addr_buf[2] = { IMX208_OTP_BASE >> 8, IMX208_OTP_BASE & 0xff };  in imx208_read_otp()
774 	int ret = 0;  in imx208_read_otp()
790 	msgs[0].addr = client->addr;  in imx208_read_otp()
791 	msgs[0].flags = 0;  in imx208_read_otp()
792 	msgs[0].len = ARRAY_SIZE(addr_buf);  in imx208_read_otp()
793 	msgs[0].buf = addr_buf;  in imx208_read_otp()
804 		ret = 0;  in imx208_read_otp()
858 				       0, link_freq_menu_items);  in imx208_init_controls()
863 	pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);  in imx208_init_controls()
896 					  V4L2_CID_HFLIP, 0, 1, 1, 0);  in imx208_init_controls()
900 					  V4L2_CID_VFLIP, 0, 1, 1, 0);  in imx208_init_controls()
913 				     0, 0, imx208_test_pattern_menu);  in imx208_init_controls()
924 	return 0;  in imx208_init_controls()
943 	u32 val = 0;  in imx208_probe()
971 	imx208->cur_mode = &supported_modes[0];  in imx208_probe()
993 	if (ret < 0)  in imx208_probe()
1008 	return 0;  in imx208_probe()