Lines Matching +full:pixel +full:- +full:array

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
37  * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39  * A single branch front-end of the CCS PLL tree.
41  * @pre_pll_clk_div: Pre-PLL clock divisor
54  * struct ccs_pll_branch_bk - CCS PLL configuration (back)
56  * A single branch back-end of the CCS PLL tree.
59  * @pix_clk_div: Pixel clock divider
61  * @pix_clk_freq_hz: Pixel clock frequency
71  * struct ccs_pll - Full CCS PLL configuration
78  * @csi2: CSI-2 related parameters
79  * @csi2.lanes: The number of the CSI-2 data lanes (input)
84  * @bits_per_pixel: Bits per pixel on the output data bus (input)
90  * @vt_fr: Video timing front-end configuration (output)
91  * @vt_bk: Video timing back-end configuration (output)
92  * @op_fr: Operational timing front-end configuration (output)
93  * @op_bk: Operational timing back-end configuration (output)
94  * @pixel_rate_csi: Pixel rate on the output data bus (output)
95  * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
127  * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
129  * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
130  * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
150  * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
156  * @min_pix_clk_div: Minimum pixel clock divider
157  * @max_pix_clk_div: Maximum pixel clock divider
158  * @min_pix_clk_freq_hz: Minimum pixel clock frequency
159  * @max_pix_clk_freq_hz: Maximum pixel clock frequency
173  * struct ccs_pll_limits - CCS PLL limits
177  * @vt_fr: Video timing front-end limits
178  * @vt_bk: Video timing back-end limits
179  * @op_fr: Operational timing front-end limits
180  * @op_bk: Operational timing back-end limits
202  * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters