Lines Matching +full:0 +full:x1fff
52 ADV748X_PORT_AIN0 = 0,
209 #define ADV748X_IO_PD 0x00 /* power down controls */
212 #define ADV748X_IO_REG_01 0x01 /* pwrdn{2}b, prog_xtal_freq */
217 #define ADV748X_IO_REG_04 0x04
218 #define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */
220 #define ADV748X_IO_DATAPATH 0x03 /* datapath cntrl */
221 #define ADV748X_IO_DATAPATH_VFREQ_M 0x70
224 #define ADV748X_IO_VID_STD 0x05
226 #define ADV748X_IO_10 0x10 /* io_reg_10 */
232 #define ADV748X_IO_CHIP_REV_ID_1 0xdf
233 #define ADV748X_IO_CHIP_REV_ID_2 0xe0
235 #define ADV748X_IO_REG_F2 0xf2
236 #define ADV748X_IO_REG_F2_READ_AUTO_INC BIT(0)
239 #define ADV748X_IO_SLAVE_ADDR_BASE 0xf2
242 * The ADV748x_Recommended_Settings_PrA_2014-08-20.pdf details both 0x80 and
243 * 0xff as examples for performing a software reset.
245 #define ADV748X_IO_REG_FF 0xff
246 #define ADV748X_IO_REG_FF_MAIN_RESET 0xff
249 #define ADV748X_HDMI_LW1 0x07 /* line width_1 */
252 #define ADV748X_HDMI_LW1_WIDTH_MASK 0x1fff
254 #define ADV748X_HDMI_F0H1 0x09 /* field0 height_1 */
255 #define ADV748X_HDMI_F0H1_HEIGHT_MASK 0x1fff
257 #define ADV748X_HDMI_F1H1 0x0b /* field1 height_1 */
260 #define ADV748X_HDMI_HFRONT_PORCH 0x20 /* hsync_front_porch_1 */
261 #define ADV748X_HDMI_HFRONT_PORCH_MASK 0x1fff
263 #define ADV748X_HDMI_HSYNC_WIDTH 0x22 /* hsync_pulse_width_1 */
264 #define ADV748X_HDMI_HSYNC_WIDTH_MASK 0x1fff
266 #define ADV748X_HDMI_HBACK_PORCH 0x24 /* hsync_back_porch_1 */
267 #define ADV748X_HDMI_HBACK_PORCH_MASK 0x1fff
269 #define ADV748X_HDMI_VFRONT_PORCH 0x2a /* field0_vs_front_porch_1 */
270 #define ADV748X_HDMI_VFRONT_PORCH_MASK 0x3fff
272 #define ADV748X_HDMI_VSYNC_WIDTH 0x2e /* field0_vs_pulse_width_1 */
273 #define ADV748X_HDMI_VSYNC_WIDTH_MASK 0x3fff
275 #define ADV748X_HDMI_VBACK_PORCH 0x32 /* field0_vs_back_porch_1 */
276 #define ADV748X_HDMI_VBACK_PORCH_MASK 0x3fff
278 #define ADV748X_HDMI_TMDS_1 0x51 /* hdmi_reg_51 */
279 #define ADV748X_HDMI_TMDS_2 0x52 /* hdmi_reg_52 */
282 #define ADV748X_REPEATER_EDID_SZ 0x70 /* primary_edid_size */
285 #define ADV748X_REPEATER_EDID_CTL 0x74 /* hdcp edid controls */
286 #define ADV748X_REPEATER_EDID_CTL_EN BIT(0) /* man_edid_a_enable */
289 #define ADV748X_SDP_INSEL 0x00 /* user_map_rw_reg_00 */
291 #define ADV748X_SDP_VID_SEL 0x02 /* user_map_rw_reg_02 */
292 #define ADV748X_SDP_VID_SEL_MASK 0xf0
296 #define ADV748X_SDP_CON 0x08 /* user_map_rw_reg_08 */
297 #define ADV748X_SDP_CON_MIN 0
302 #define ADV748X_SDP_BRI 0x0a /* user_map_rw_reg_0a */
304 #define ADV748X_SDP_BRI_DEF 0
308 #define ADV748X_SDP_HUE 0x0b /* user_map_rw_reg_0b */
310 #define ADV748X_SDP_HUE_DEF 0
314 #define ADV748X_SDP_DEF 0x0c /* user_map_rw_reg_0c */
315 #define ADV748X_SDP_DEF_VAL_EN BIT(0) /* Force free run mode */
318 #define ADV748X_SDP_MAP_SEL 0x0e /* user_map_rw_reg_0e */
322 #define ADV748X_SDP_FRP 0x14
323 #define ADV748X_SDP_FRP_MASK GENMASK(2, 0)
326 #define ADV748X_SDP_SD_SAT_U 0xe3 /* user_map_rw_reg_e3 */
327 #define ADV748X_SDP_SD_SAT_V 0xe4 /* user_map_rw_reg_e4 */
328 #define ADV748X_SDP_SAT_MIN 0
333 #define ADV748X_SDP_RO_10 0x10
334 #define ADV748X_SDP_RO_10_IN_LOCK BIT(0)
337 #define ADV748X_CP_PAT_GEN 0x37 /* int_pat_gen_1 */
341 #define ADV748X_CP_CON 0x3a /* contrast_cntrl */
342 #define ADV748X_CP_CON_MIN 0 /* Minimum contrast */
347 #define ADV748X_CP_SAT 0x3b /* saturation_cntrl */
348 #define ADV748X_CP_SAT_MIN 0 /* Minimum saturation */
353 #define ADV748X_CP_BRI 0x3c /* brightness_cntrl */
355 #define ADV748X_CP_BRI_DEF 0 /* Luma is 0 */
359 #define ADV748X_CP_HUE 0x3d /* hue_cntrl */
360 #define ADV748X_CP_HUE_MIN 0 /* -90 degree */
361 #define ADV748X_CP_HUE_DEF 0 /* -90 degree */
364 #define ADV748X_CP_VID_ADJ 0x3e /* vid_adj_0 */
367 #define ADV748X_CP_DE_POS_HIGH 0x8b /* de_pos_adj_6 */
369 #define ADV748X_CP_DE_POS_END_LOW 0x8c /* de_pos_adj_7 */
370 #define ADV748X_CP_DE_POS_START_LOW 0x8d /* de_pos_adj_8 */
372 #define ADV748X_CP_VID_ADJ_2 0x91
376 #define ADV748X_CP_CLMP_POS 0xc9 /* clmp_pos_cntrl_4 */
377 #define ADV748X_CP_CLMP_POS_DIS_AUTO BIT(0) /* dis_auto_param_buff */
380 #define ADV748X_CSI_VC_REF 0x0d /* csi_tx_top_reg_0d */
383 #define ADV748X_CSI_FS_AS_LS 0x1e /* csi_tx_top_reg_1e */