Lines Matching full:txb
56 ADV748X_REGMAP_CONF("txb"),
96 [ADV748X_PAGE_TXB] = { "txb", 0x48 },
234 * TXA and TXB
358 /* AFE Requires TXA enabled, even when output to TXB */ in adv748x_link_setup()
370 /* TXB has a single data lane, no need to adjust. */ in adv748x_link_setup()
523 /* Reset TXA and TXB */ in adv748x_reset()
526 adv748x_tx_power(&state->txb, 1); in adv748x_reset()
527 adv748x_tx_power(&state->txb, 0); in adv748x_reset()
532 /* Conditionally enable TXa and TXb. */ in adv748x_reset()
537 if (is_tx_enabled(&state->txb)) { in adv748x_reset()
539 adv748x_csi2_set_virtual_channel(&state->txb, 0); in adv748x_reset()
639 adv_err(state, "TXB: Invalid number (%u) of lanes\n", in adv748x_parse_csi2_lanes()
644 state->txb.num_lanes = num_lanes; in adv748x_parse_csi2_lanes()
645 state->txb.active_lanes = num_lanes; in adv748x_parse_csi2_lanes()
646 adv_dbg(state, "TXB: using %u lanes\n", state->txb.num_lanes); in adv748x_parse_csi2_lanes()
690 /* Store number of CSI-2 lanes used for TXA and TXB. */ in adv748x_parse_dt()
732 state->txa.state = state->txb.state = state; in adv748x_probe()
734 state->txb.page = ADV748X_PAGE_TXB; in adv748x_probe()
736 state->txb.port = ADV748X_PORT_TXB; in adv748x_probe()
793 /* Initialise TXB */ in adv748x_probe()
794 ret = adv748x_csi2_init(state, &state->txb); in adv748x_probe()
796 adv_err(state, "Failed to probe TXB"); in adv748x_probe()
826 adv748x_csi2_cleanup(&state->txb); in adv748x_remove()