33  * @tx_base:			Base address of the CPUCP tx registers
34  * @rx_base:			Base address of the CPUCP rx registers
50 	struct qcom_cpucp_mbox *cpucp = data;  in qcom_cpucp_mbox_irq_fn()  local
54 	status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);  in qcom_cpucp_mbox_irq_fn()
57 		u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF);  in qcom_cpucp_mbox_irq_fn()
58 		struct mbox_chan *chan = &cpucp->chans[i];  in qcom_cpucp_mbox_irq_fn()
65 		writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);  in qcom_cpucp_mbox_irq_fn()
74 	struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox);  in qcom_cpucp_mbox_startup()  local
78 	val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);  in qcom_cpucp_mbox_startup()
80 	writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);  in qcom_cpucp_mbox_startup()
87 	struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox);  in qcom_cpucp_mbox_shutdown()  local
91 	val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);  in qcom_cpucp_mbox_shutdown()
93 	writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);  in qcom_cpucp_mbox_shutdown()
98 	struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox);  in qcom_cpucp_mbox_send_data()  local
102 	writel(*val, cpucp->tx_base + APSS_CPUCP_TX_MBOX_CMD(chan_id) + APSS_CPUCP_MBOX_CMD_OFF);  in qcom_cpucp_mbox_send_data()
116 	struct qcom_cpucp_mbox *cpucp;  in qcom_cpucp_mbox_probe()  local
120 	cpucp = devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL);  in qcom_cpucp_mbox_probe()
121 	if (!cpucp)  in qcom_cpucp_mbox_probe()
124 	cpucp->rx_base = devm_of_iomap(dev, dev->of_node, 0, NULL);  in qcom_cpucp_mbox_probe()
125 	if (IS_ERR(cpucp->rx_base))  in qcom_cpucp_mbox_probe()
126 		return PTR_ERR(cpucp->rx_base);  in qcom_cpucp_mbox_probe()
128 	cpucp->tx_base = devm_of_iomap(dev, dev->of_node, 1, NULL);  in qcom_cpucp_mbox_probe()
129 	if (IS_ERR(cpucp->tx_base))  in qcom_cpucp_mbox_probe()
130 		return PTR_ERR(cpucp->tx_base);  in qcom_cpucp_mbox_probe()
132 	writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);  in qcom_cpucp_mbox_probe()
133 	writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);  in qcom_cpucp_mbox_probe()
134 	writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP);  in qcom_cpucp_mbox_probe()
141 			       IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND, "apss_cpucp_mbox", cpucp);  in qcom_cpucp_mbox_probe()
145 	writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP);  in qcom_cpucp_mbox_probe()
147 	mbox = &cpucp->mbox;  in qcom_cpucp_mbox_probe()
150 	mbox->chans = cpucp->chans;  in qcom_cpucp_mbox_probe()
161 	{ .compatible = "qcom,x1e80100-cpucp-mbox" },
186 MODULE_DESCRIPTION("QTI CPUCP MBOX Driver");