Lines Matching +full:flen +full:- +full:gpios
1 /* SPDX-License-Identifier: GPL-2.0 */
33 * also registers are assigned differen for HFC-4s/8s and HFC-E1
41 struct dchannel *dch; /* link if channel is a D-channel */
42 struct bchannel *bch; /* link if channel is a B-channel */
45 int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */
58 int Zfill; /* rx-fifo level on last hfcmulti_tx */
84 #define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */
85 #define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */
91 #define HFC_CFG_DTMF 9 /* enable DTMF-detection */
92 #define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */
95 #define HFC_TYPE_E1 1 /* controller is HFC-E1 */
96 #define HFC_TYPE_4S 4 /* controller is HFC-4S */
97 #define HFC_TYPE_8S 8 /* controller is HFC-8S */
116 #define HFC_CHIP_PLXSD 14 /* whether we have a Speech-Design PLX */
194 struct hfcm_hw hw; /* remember data of write-only-registers */
197 int masterclk; /* port that provides master clock -1=off */
201 int Flen; /* F-buffer size */ member
202 int Zlen; /* Z-buffer size (must be int for calculation)*/
204 int Zmin; /* Z-buffer offset */
219 /* showing led-states) */
237 * is located on the hfc-channel.
238 * the bch->channel is equvalent to the hfc-channel
244 /* PLX GPIOs */
291 * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1
471 * BIT SETTING FOR HFC-4S/8S AND HFC-E1
1160 {"A_FIFO_DATA0-2", 0x80},
1161 {"A_FIFO_DATA0-2_NOINC", 0x84},
1223 {"A_FIFO_DATA0-2", 0x80},
1224 {"A_FIFO_DATA0-2_NOINC", 0x84},