1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
47 #define pin_to_hwirq(r, p)	((r)->parent_base + (p) - (r)->pin_base)
72 static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)  in pdc_x1e_irq_enable_write()  argument
79 		/* Use previous DRV (client) region and shift to bank 3-4 */  in pdc_x1e_irq_enable_write()
84 		/* Use our own region and shift to bank 0-2 */  in pdc_x1e_irq_enable_write()
86 		bank -= 2;  in pdc_x1e_irq_enable_write()
97 	pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable);  in pdc_x1e_irq_enable_write()
102 	unsigned long enable;  in __pdc_enable_intr()  local
110 		enable = pdc_reg_read(IRQ_ENABLE_BANK, index);  in __pdc_enable_intr()
111 		__assign_bit(mask, &enable, on);  in __pdc_enable_intr()
114 			pdc_x1e_irq_enable_write(index, enable);  in __pdc_enable_intr()
116 			pdc_reg_write(IRQ_ENABLE_BANK, index, enable);  in __pdc_enable_intr()
118 		enable = pdc_reg_read(IRQ_i_CFG, pin_out);  in __pdc_enable_intr()
119 		__assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);  in __pdc_enable_intr()
120 		pdc_reg_write(IRQ_i_CFG, pin_out, enable);  in __pdc_enable_intr()
129 	__pdc_enable_intr(d->hwirq, on);  in pdc_enable_intr()
146  * GIC does not handle falling edge or active low. To allow falling edge and
147  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
148  * falling edge into a rising edge and active low into an active high.
151  * Level sensitive active low    LOW
155  * Level sensitive active High   HIGH
171  * @d: the interrupt data
206 		return -EINVAL;  in qcom_pdc_gic_set_type()
209 	old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);  in qcom_pdc_gic_set_type()
211 	pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);  in qcom_pdc_gic_set_type()
265 			  unsigned int nr_irqs, void *data)  in qcom_pdc_alloc()  argument
267 	struct irq_fwspec *fwspec = data;  in qcom_pdc_alloc()
288 		return irq_domain_disconnect_hierarchy(domain->parent, virq);  in qcom_pdc_alloc()
296 	parent_fwspec.fwnode      = domain->parent->fwnode;  in qcom_pdc_alloc()
316 	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));  in pdc_setup_pin_mapping()
318 		return -EINVAL;  in pdc_setup_pin_mapping()
324 		return -ENOMEM;  in pdc_setup_pin_mapping()
328 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
333 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
338 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
362 		return -EINVAL;  in qcom_pdc_init()
376 	if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) {  in qcom_pdc_init()
377 		pdc_prev_base = ioremap(res.start - PDC_DRV_OFFSET, IRQ_ENABLE_BANK_MAX);  in qcom_pdc_init()
380 			return -ENXIO;  in qcom_pdc_init()
389 		ret = -ENXIO;  in qcom_pdc_init()
398 		ret = -ENXIO;  in qcom_pdc_init()
404 		pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);  in qcom_pdc_init()
415 		ret = -ENOMEM;  in qcom_pdc_init()