1 // SPDX-License-Identifier: GPL-2.0
3  * Renesas RZ/V2H(P) ICU Driver
5  * Based on irq-renesas-rzg2l.c
84  * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
99 	return data->domain->host_data;  in irq_data_to_priv()
109 	scoped_guard(raw_spinlock, &priv->lock) {  in rzv2h_icu_eoi()
111 			tintirq_nr = hw_irq - ICU_TINT_START;  in rzv2h_icu_eoi()
114 				writel_relaxed(bit, priv->base + ICU_TSCLR);  in rzv2h_icu_eoi()
116 			tintirq_nr = hw_irq - ICU_IRQ_START;  in rzv2h_icu_eoi()
119 				writel_relaxed(bit, priv->base + ICU_ISCLR);  in rzv2h_icu_eoi()
121 			writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR);  in rzv2h_icu_eoi()
137 	tint_nr = hw_irq - ICU_TINT_START;  in rzv2h_tint_irq_endisable()
141 	guard(raw_spinlock)(&priv->lock);  in rzv2h_tint_irq_endisable()
142 	tssr = readl_relaxed(priv->base + ICU_TSSR(k));  in rzv2h_tint_irq_endisable()
147 	writel_relaxed(tssr, priv->base + ICU_TSSR(k));  in rzv2h_tint_irq_endisable()
177 		return -EINVAL;  in rzv2h_nmi_set_type()
180 	writel_relaxed(sense, priv->base + ICU_NITSR);  in rzv2h_nmi_set_type()
187 	unsigned int irq_nr = hwirq - ICU_IRQ_START;  in rzv2h_clear_irq_int()
191 	isctr = readl_relaxed(priv->base + ICU_ISCTR);  in rzv2h_clear_irq_int()
192 	iitsr = readl_relaxed(priv->base + ICU_IITSR);  in rzv2h_clear_irq_int()
197 	 * interrupt signal is de-asserted by the source of the interrupt request, therefore clear  in rzv2h_clear_irq_int()
201 		writel_relaxed(bit, priv->base + ICU_ISCLR);  in rzv2h_clear_irq_int()
208 	u32 irq_nr = hwirq - ICU_IRQ_START;  in rzv2h_irq_set_type()
229 		return -EINVAL;  in rzv2h_irq_set_type()
232 	guard(raw_spinlock)(&priv->lock);  in rzv2h_irq_set_type()
233 	iitsr = readl_relaxed(priv->base + ICU_IITSR);  in rzv2h_irq_set_type()
237 	writel_relaxed(iitsr, priv->base + ICU_IITSR);  in rzv2h_irq_set_type()
244 	unsigned int tint_nr = hwirq - ICU_TINT_START;  in rzv2h_clear_tint_int()
250 	tsctr = readl_relaxed(priv->base + ICU_TSCTR);  in rzv2h_clear_tint_int()
251 	titsr = readl_relaxed(priv->base + ICU_TITSR(k));  in rzv2h_clear_tint_int()
260 		writel_relaxed(bit, priv->base + ICU_TSCLR);  in rzv2h_clear_tint_int()
290 		return -EINVAL;  in rzv2h_tint_set_type()
295 		return -EINVAL;  in rzv2h_tint_set_type()
300 	tint_nr = hwirq - ICU_TINT_START;  in rzv2h_tint_set_type()
309 	guard(raw_spinlock)(&priv->lock);  in rzv2h_tint_set_type()
311 	tssr = readl_relaxed(priv->base + ICU_TSSR(tssr_k));  in rzv2h_tint_set_type()
315 	writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k));  in rzv2h_tint_set_type()
317 	titsr = readl_relaxed(priv->base + ICU_TITSR(titsr_k));  in rzv2h_tint_set_type()
321 	writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k));  in rzv2h_tint_set_type()
325 	writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k));  in rzv2h_tint_set_type()
349 	.name			= "rzv2h-icu",
366 	struct rzv2h_icu_priv *priv = domain->host_data;  in rzv2h_icu_alloc()
378 	 * fwspec->param[0].  in rzv2h_icu_alloc()
379 	 * hwirq is embedded in bits 0-15.  in rzv2h_icu_alloc()
380 	 * TINT is embedded in bits 16-31.  in rzv2h_icu_alloc()
387 			return -EINVAL;  in rzv2h_icu_alloc()
390 	if (hwirq > (ICU_NUM_IRQ - 1))  in rzv2h_icu_alloc()
391 		return -EINVAL;  in rzv2h_icu_alloc()
393 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip,  in rzv2h_icu_alloc()
398 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);  in rzv2h_icu_alloc()
418 		of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]);  in rzv2h_icu_parse_interrupts()
434 		return -ENODEV;  in rzv2h_icu_init()
438 		dev_err(&pdev->dev, "cannot find parent domain\n");  in rzv2h_icu_init()
439 		ret = -ENODEV;  in rzv2h_icu_init()
443 	rzv2h_icu_data = devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);  in rzv2h_icu_init()
445 		ret = -ENOMEM;  in rzv2h_icu_init()
449 	rzv2h_icu_data->irqchip = &rzv2h_icu_chip;  in rzv2h_icu_init()
451 	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);  in rzv2h_icu_init()
452 	if (IS_ERR(rzv2h_icu_data->base)) {  in rzv2h_icu_init()
453 		ret = PTR_ERR(rzv2h_icu_data->base);  in rzv2h_icu_init()
459 		dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);  in rzv2h_icu_init()
463 	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in rzv2h_icu_init()
471 		dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);  in rzv2h_icu_init()
475 	pm_runtime_enable(&pdev->dev);  in rzv2h_icu_init()
476 	ret = pm_runtime_resume_and_get(&pdev->dev);  in rzv2h_icu_init()
478 		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);  in rzv2h_icu_init()
482 	raw_spin_lock_init(&rzv2h_icu_data->lock);  in rzv2h_icu_init()
487 		dev_err(&pdev->dev, "failed to add irq domain\n");  in rzv2h_icu_init()
488 		ret = -ENOMEM;  in rzv2h_icu_init()
494 	 * positive. We still need &pdev->dev after successfully returning from this function.  in rzv2h_icu_init()
499 	pm_runtime_put(&pdev->dev);  in rzv2h_icu_init()
501 	pm_runtime_disable(&pdev->dev);  in rzv2h_icu_init()
504 	put_device(&pdev->dev);  in rzv2h_icu_init()
510 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
513 MODULE_DESCRIPTION("Renesas RZ/V2H(P) ICU Driver");