6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
44 #define GIC_HWIRQ_TO_LOCAL(x)	((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x)	((x) - GIC_SHARED_HWIRQ_BASE)
98  * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
109 	for ((cpu) = __gic_with_next_online_cpu(-1);	\
115  * gic_irq_lock_cluster() - Lock redirect block access to IRQ's cluster
186 	irq -= GIC_PIN_TO_VEC_OFFSET;  in gic_bind_eic_interrupt()
217 			return -1;  in gic_get_c0_perfcount_int()
229 			return -1;  in gic_get_c0_fdc_int()
243 	/* Get per-cpu bitmaps */  in gic_handle_shared_int()
267 	unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_mask_irq()
281 	unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_unmask_irq()
298 	unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_ack_irq()
313 	irq = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_set_type()
371 	unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_set_affinity()
382 		return -EINVAL;  in gic_set_affinity()
404 	 * Update effective affinity - after this gic_irq_lock_cluster() will  in gic_set_affinity()
488 	int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_mask_local_irq()
495 	int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_unmask_local_irq()
514 	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_mask_local_irq_all_vpes()
516 	cd->mask = false;  in gic_mask_local_irq_all_vpes()
530 	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_unmask_local_irq_all_vpes()
532 	cd->mask = true;  in gic_unmask_local_irq_all_vpes()
557 		write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);  in gic_all_vpes_irq_cpu_online()
558 		if (cd->mask)  in gic_all_vpes_irq_cpu_online()
617 		return -EINVAL;  in gic_irq_domain_xlate()
624 		return -EINVAL;  in gic_irq_domain_xlate()
640 		/* verify that shared irqs don't conflict with an IPI irq */  in gic_irq_domain_map()
642 			return -EBUSY;  in gic_irq_domain_map()
659 	 * If adding support for more per-cpu interrupts, keep the  in gic_irq_domain_map()
672 		cd->map = map;  in gic_irq_domain_map()
695 		return -EPERM;  in gic_irq_domain_map()
711 	if (fwspec->param[0] == GIC_SHARED)  in gic_irq_domain_alloc()
712 		hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);  in gic_irq_domain_alloc()
714 		hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);  in gic_irq_domain_alloc()
757 		return -ENOMEM;  in gic_ipi_domain_alloc()
762 			return -EBUSY;  in gic_ipi_domain_alloc()
777 		ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,  in gic_ipi_domain_alloc()
824 		is_ipi = d->bus_token == bus_token;  in gic_ipi_domain_match()
825 		return (!node || to_of_node(d->fwnode) == node) && is_ipi;  in gic_ipi_domain_match()
849 		pr_err("Failed to add IPI domain");  in gic_register_ipi_domain()
850 		return -ENXIO;  in gic_register_ipi_domain()
856 	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {  in gic_register_ipi_domain()
864 		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);  in gic_register_ipi_domain()
900 	unsigned long reserved;  in gic_of_init()  local
908 	reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);  in gic_of_init()
909 	while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",  in gic_of_init()
911 		reserved |= BIT(cpu_vec);  in gic_of_init()
913 	cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));  in gic_of_init()
915 		pr_err("No CPU vectors available\n");  in gic_of_init()
916 		return -ENODEV;  in gic_of_init()
922 		 * in the device-tree.  in gic_of_init()
932 			return -ENODEV;  in gic_of_init()
948 		return -ENOMEM;  in gic_of_init()
961 		gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;  in gic_of_init()
971 		return -ENXIO;  in gic_of_init()
983 	 * Otherwise, the IPI set up will be erased if we move code  in gic_of_init()