Lines Matching +full:fiq +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
26 #include <linux/irqchip/arm-gic-common.h>
27 #include <linux/irqchip/arm-gic-v3.h>
28 #include <linux/irqchip/arm-gic-v3-prio.h>
29 #include <linux/irqchip/irq-partition-percpu.h>
32 #include <linux/arm-smccc.h>
39 #include "irq-gic-common.h"
98 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
102 * When security is enabled, non-secure priority values from the (re)distributor
106 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
108 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
112 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
114 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
140 * setting the highest possible, non-zero priority in PMR. in gic_has_group0()
142 * If SCR_EL3.FIQ is set, the priority gets shifted down in in gic_has_group0()
144 * actual priority in the non-secure range. In the process, it in gic_has_group0()
149 gic_write_pmr(BIT(8 - gic_get_pribits())); in gic_has_group0()
194 * and if Group 0 interrupts can be delivered to Linux in the non-secure in gic_prio_init()
195 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the in gic_prio_init()
198 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Distributor in gic_prio_init()
199 * ------------------------------------------------------- in gic_prio_init()
200 * 1 | - | unchanged | unchanged in gic_prio_init()
201 * ------------------------------------------------------- in gic_prio_init()
202 * 0 | 1 | non-secure | non-secure in gic_prio_init()
203 * ------------------------------------------------------- in gic_prio_init()
204 * 0 | 0 | unchanged | non-secure in gic_prio_init()
206 * In the non-secure view reads and writes are modified: in gic_prio_init()
208 * - A value written is right-shifted by one and the MSB is set, in gic_prio_init()
209 * forcing the priority into the non-secure range. in gic_prio_init()
211 * - A value read is left-shifted by one. in gic_prio_init()
218 * be in the non-secure range, we program the non-secure values into in gic_prio_init()
226 pr_info("GICD_CTRL.DS=%d, SCR_EL3.FIQ=%d\n", in gic_prio_init()
239 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
277 return __get_intid_range(d->hwirq); in get_intid_range()
299 * For the erratum T241-FABRIC-4, read accesses to GICD_In{E} in gic_dist_base_alias()
304 * Chip0 = 32-351 in gic_dist_base_alias()
305 * Chip1 = 352-671 in gic_dist_base_alias()
306 * Chip2 = 672-991 in gic_dist_base_alias()
307 * Chip3 = 4096-4415 in gic_dist_base_alias()
311 chip = (hwirq - 32) / 320; in gic_dist_base_alias()
331 /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
336 /* SPI -> dist_base */ in gic_dist_base()
351 if (ret == -ETIMEDOUT) in gic_do_wait_for_rwp()
395 if (ret == -ETIMEDOUT) { in gic_enable_redist()
410 *index = d->hwirq; in convert_offset_index()
418 *index = d->hwirq - EPPI_BASE_INTID + 32; in convert_offset_index()
421 *index = d->hwirq - ESPI_BASE_INTID; in convert_offset_index()
450 *index = d->hwirq; in convert_offset_index()
526 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ in gic_irq_set_irqchip_state()
527 return -EINVAL; in gic_irq_set_irqchip_state()
547 return -EINVAL; in gic_irq_set_irqchip_state()
553 * Force read-back to guarantee that the active state has taken in gic_irq_set_irqchip_state()
554 * effect, and won't race with a guest-driven deactivation. in gic_irq_set_irqchip_state()
564 if (d->hwirq >= 8192) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
565 return -EINVAL; in gic_irq_get_irqchip_state()
581 return -EINVAL; in gic_irq_get_irqchip_state()
601 return hwirq - 16; in __gic_get_ppi_index()
603 return hwirq - EPPI_BASE_INTID + 16; in __gic_get_ppi_index()
616 return hwirq - EPPI_BASE_INTID + 32; in __gic_get_rdist_index()
624 return __gic_get_rdist_index(d->hwirq); in gic_get_rdist_index()
629 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_setup()
632 return -EINVAL; in gic_irq_nmi_setup()
635 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_setup()
636 return -EINVAL; in gic_irq_nmi_setup()
644 return -EINVAL; in gic_irq_nmi_setup()
656 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; in gic_irq_nmi_setup()
659 desc->handle_irq = handle_fasteoi_nmi; in gic_irq_nmi_setup()
669 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_teardown()
675 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_teardown()
692 desc->handle_irq = handle_percpu_devid_irq; in gic_irq_nmi_teardown()
694 desc->handle_irq = handle_fasteoi_irq; in gic_irq_nmi_teardown()
762 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; in gic_set_type()
767 return -EINVAL; in gic_set_type()
789 return -EINVAL; in gic_irq_set_vcpu_affinity()
888 WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr); in __gic_handle_nmi()
984 * Configure SPIs as non-secure Group-1. This will only matter in gic_dist_init()
1035 int ret = -ENODEV; in gic_iterate_rdists()
1069 return ret ? -ENODEV : 0; in gic_iterate_rdists()
1091 u64 offset = ptr - region->redist_base; in __gic_populate_rdist()
1092 raw_spin_lock_init(&gic_data_rdist()->rd_lock); in __gic_populate_rdist()
1094 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
1098 (int)(region - gic_data.redist_regions), in __gic_populate_rdist()
1099 &gic_data_rdist()->phys_base); in __gic_populate_rdist()
1113 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", in gic_populate_rdist()
1116 return -ENODEV; in gic_populate_rdist()
1125 /* Boot-time cleanup */ in __gic_update_rdist_properties()
1145 * doc says... :-/ And CTLR.IR implies another subset of DirectLPI in __gic_update_rdist_properties()
1158 /* Detect non-sensical configurations */ in __gic_update_rdist_properties()
1232 * any pre-emptive interrupts from working at all). Writing a zero in gic_cpu_sys_reg_init()
1301 * - The write is ignored. in gic_cpu_sys_reg_init()
1302 * - The RS field is treated as 0. in gic_cpu_sys_reg_init()
1341 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1364 return -EINVAL; in gic_check_rdist()
1400 cpu--; in gic_compute_target_list()
1432 if (WARN_ON(d->hwirq >= 16)) in gic_ipi_send_mask()
1446 gic_send_sgi(cluster_id, tlist, d->hwirq); in gic_ipi_send_mask()
1469 /* Register all 8 non-secure SGIs */ in gic_smp_init()
1492 return -EINVAL; in gic_set_affinity()
1495 return -EINVAL; in gic_set_affinity()
1610 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1616 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1624 return -EPERM; in gic_irq_domain_map()
1625 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1630 return -EPERM; in gic_irq_domain_map()
1643 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { in gic_irq_domain_translate()
1644 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1649 if (is_of_node(fwspec->fwnode)) { in gic_irq_domain_translate()
1650 if (fwspec->param_count < 3) in gic_irq_domain_translate()
1651 return -EINVAL; in gic_irq_domain_translate()
1653 switch (fwspec->param[0]) { in gic_irq_domain_translate()
1655 *hwirq = fwspec->param[1] + 32; in gic_irq_domain_translate()
1658 *hwirq = fwspec->param[1] + 16; in gic_irq_domain_translate()
1661 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; in gic_irq_domain_translate()
1664 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; in gic_irq_domain_translate()
1667 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1670 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1671 if (fwspec->param[1] >= 16) in gic_irq_domain_translate()
1672 *hwirq += EPPI_BASE_INTID - 16; in gic_irq_domain_translate()
1677 return -EINVAL; in gic_irq_domain_translate()
1680 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gic_irq_domain_translate()
1687 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); in gic_irq_domain_translate()
1691 if (is_fwnode_irqchip(fwspec->fwnode)) { in gic_irq_domain_translate()
1692 if(fwspec->param_count != 2) in gic_irq_domain_translate()
1693 return -EINVAL; in gic_irq_domain_translate()
1695 if (fwspec->param[0] < 16) { in gic_irq_domain_translate()
1697 fwspec->param[0]); in gic_irq_domain_translate()
1698 return -EINVAL; in gic_irq_domain_translate()
1701 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1702 *type = fwspec->param[1]; in gic_irq_domain_translate()
1708 return -EINVAL; in gic_irq_domain_translate()
1752 if (!is_of_node(fwspec->fwnode)) in fwspec_is_partitioned_ppi()
1755 if (fwspec->param_count < 4 || !fwspec->param[3]) in fwspec_is_partitioned_ppi()
1773 if (fwspec->fwnode != d->fwnode) in gic_irq_domain_select()
1777 if (!fwspec->param_count) in gic_irq_domain_select()
1778 return d->bus_token == bus_token; in gic_irq_domain_select()
1781 if (!is_of_node(fwspec->fwnode)) in gic_irq_domain_select()
1792 * If this is a PPI and we have a 4th (non-null) parameter, in gic_irq_domain_select()
1817 return -ENOMEM; in partition_domain_translate()
1819 np = of_find_node_by_phandle(fwspec->param[3]); in partition_domain_translate()
1821 return -EINVAL; in partition_domain_translate()
1834 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in partition_domain_translate()
1848 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; in gic_enable_quirk_msm8996()
1857 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; in gic_enable_quirk_cavium_38539()
1867 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite in gic_enable_quirk_hip06_07()
1869 * that GIC-600 doesn't have ESPI, so nothing to do in that case. in gic_enable_quirk_hip06_07()
1873 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { in gic_enable_quirk_hip06_07()
1875 d->rdists.gicd_typer &= ~GENMASK(9, 8); in gic_enable_quirk_hip06_07()
1897 /* Find the chips based on GICR regions PHYS addr */ in gic_enable_quirk_nvidia_t241()
1923 d->flags |= FLAGS_WORKAROUND_ASR_ERRATUM_8601001; in gic_enable_quirk_asr8601()
1939 d->flags |= FLAGS_WORKAROUND_INSECURE; in gic_enable_quirk_rk3399()
1950 d->rdists.flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; in rd_set_non_coherent()
1957 .compatible = "qcom,msm8996-gic-v3",
1962 .compatible = "asr,asr8601-gic-v3",
1981 * - ThunderX: CN88xx
1982 * - OCTEON TX: CN83xx, CN81xx
1983 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1991 .desc = "GICv3: NVIDIA erratum T241-FABRIC-4",
1998 * GIC-700: 2941627 workaround - IP variant [0,1]
2008 * GIC-700: 2941627 workaround - IP variant [2]
2016 .desc = "GICv3: non-coherent attribute",
2017 .property = "dma-noncoherent",
2045 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", in gic_enable_nmi_support()
2088 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); in gic_init_bases()
2102 /* Disable GICv4.x features for the erratum T241-FABRIC-4 */ in gic_init_bases()
2110 err = -ENOMEM; in gic_init_bases()
2159 return -ENODEV; in gic_validate_dist_version()
2172 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); in gic_populate_ppi_partitions()
2195 part->partition_id = of_node_to_fwnode(child_part); in gic_populate_ppi_partitions()
2226 cpumask_set_cpu(cpu, &part->mask); in gic_populate_ppi_partitions()
2301 gic_request_region(res->start, resource_size(res), name); in gic_of_iomap()
2304 return base ?: IOMEM_ERR_PTR(-ENOMEM); in gic_of_iomap()
2331 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) in gic_of_init()
2337 err = -ENOMEM; in gic_of_init()
2345 err = -ENODEV; in gic_of_init()
2351 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) in gic_of_init()
2357 nr_redist_regions, redist_stride, &node->fwnode); in gic_of_init()
2377 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2411 redist_base = ioremap(redist->base_address, redist->length); in gic_acpi_parse_madt_redist()
2413 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
2414 return -ENOMEM; in gic_acpi_parse_madt_redist()
2418 (redist->flags & ACPI_MADT_GICR_NON_COHERENT)) in gic_acpi_parse_madt_redist()
2421 gic_request_region(redist->base_address, redist->length, "GICR"); in gic_acpi_parse_madt_redist()
2423 gic_acpi_register_redist(redist->base_address, redist_base); in gic_acpi_parse_madt_redist()
2438 if (!(gicc->flags & (ACPI_MADT_ENABLED | ACPI_MADT_GICC_ONLINE_CAPABLE))) in gic_acpi_parse_madt_gicc()
2444 * Virtual hotplug systems can use the MADT's "always-on" GICR entries. in gic_acpi_parse_madt_gicc()
2447 if (!(gicc->flags & ACPI_MADT_ENABLED)) { in gic_acpi_parse_madt_gicc()
2448 int cpu = get_cpu_for_acpi_id(gicc->uid); in gic_acpi_parse_madt_gicc()
2456 redist_base = ioremap(gicc->gicr_base_address, size); in gic_acpi_parse_madt_gicc()
2458 return -ENOMEM; in gic_acpi_parse_madt_gicc()
2459 gic_request_region(gicc->gicr_base_address, size, "GICR"); in gic_acpi_parse_madt_gicc()
2462 (gicc->flags & ACPI_MADT_GICC_NON_COHERENT)) in gic_acpi_parse_madt_gicc()
2465 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); in gic_acpi_parse_madt_gicc()
2487 return -ENODEV; in gic_acpi_collect_gicr_base()
2510 if (gicc->flags & ACPI_MADT_ENABLED && gicc->gicr_base_address) in gic_acpi_match_gicc()
2549 if (dist->version != ape->driver_data) in acpi_validate_gic_table()
2569 if (!(gicc->flags & in gic_acpi_parse_virt_madt_gicc()
2573 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? in gic_acpi_parse_virt_madt_gicc()
2579 acpi_data.maint_irq = gicc->vgic_interrupt; in gic_acpi_parse_virt_madt_gicc()
2581 acpi_data.vcpu_base = gicc->gicv_base_address; in gic_acpi_parse_virt_madt_gicc()
2589 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || in gic_acpi_parse_virt_madt_gicc()
2591 (acpi_data.vcpu_base != gicc->gicv_base_address)) in gic_acpi_parse_virt_madt_gicc()
2592 return -EINVAL; in gic_acpi_parse_virt_madt_gicc()
2633 vcpu->flags = IORESOURCE_MEM; in gic_acpi_setup_kvm_info()
2634 vcpu->start = acpi_data.vcpu_base; in gic_acpi_setup_kvm_info()
2635 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; in gic_acpi_setup_kvm_info()
2659 acpi_data.dist_base = ioremap(dist->base_address, in gic_acpi_init()
2663 return -ENOMEM; in gic_acpi_init()
2665 gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD"); in gic_acpi_init()
2677 err = -ENOMEM; in gic_acpi_init()
2685 gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address); in gic_acpi_init()
2687 err = -ENOMEM; in gic_acpi_init()
2691 err = gic_init_bases(dist->base_address, acpi_data.dist_base, in gic_acpi_init()