1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2014-2024 Broadcom
34 /* Register offsets in the L2 latched interrupt controller */
44 /* Register offsets in the L2 level interrupt controller */
48 	.cpu_clear		= -1, /* Register not present */
54 /* L2 intc private data structure */
73 	status = irq_reg_readl(b->gc, b->status_offset) &  in brcmstb_l2_intc_irq_handle()
74 		~(irq_reg_readl(b->gc, b->mask_offset));  in brcmstb_l2_intc_irq_handle()
77 		raw_spin_lock(&desc->lock);  in brcmstb_l2_intc_irq_handle()
79 		raw_spin_unlock(&desc->lock);  in brcmstb_l2_intc_irq_handle()
84 		irq = ffs(status) - 1;  in brcmstb_l2_intc_irq_handle()
86 		generic_handle_domain_irq(b->domain, irq);  in brcmstb_l2_intc_irq_handle()
99 	struct brcmstb_l2_intc_data *b = gc->private;  in __brcmstb_l2_intc_suspend()
105 		b->saved_mask = irq_reg_readl(gc, ct->regs.mask);  in __brcmstb_l2_intc_suspend()
107 	if (b->can_wake) {  in __brcmstb_l2_intc_suspend()
109 		irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);  in __brcmstb_l2_intc_suspend()
110 		irq_reg_writel(gc, gc->wake_active, ct->regs.enable);  in __brcmstb_l2_intc_suspend()
129 	struct brcmstb_l2_intc_data *b = gc->private;  in brcmstb_l2_intc_resume()
133 	if (ct->chip.irq_ack) {  in brcmstb_l2_intc_resume()
134 		/* Clear unmasked non-wakeup interrupts */  in brcmstb_l2_intc_resume()
135 		irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,  in brcmstb_l2_intc_resume()
136 				ct->regs.ack);  in brcmstb_l2_intc_resume()
140 	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);  in brcmstb_l2_intc_resume()
141 	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);  in brcmstb_l2_intc_resume()
161 		return -ENOMEM;  in brcmstb_l2_intc_of_init()
165 		pr_err("failed to remap intc L2 registers\n");  in brcmstb_l2_intc_of_init()
166 		ret = -ENOMEM;  in brcmstb_l2_intc_of_init()
171 	writel(0xffffffff, base + init_params->cpu_mask_set);  in brcmstb_l2_intc_of_init()
174 	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");  in brcmstb_l2_intc_of_init()
175 	if (!data->can_wake && (init_params->cpu_clear >= 0))  in brcmstb_l2_intc_of_init()
176 		writel(0xffffffff, base + init_params->cpu_clear);  in brcmstb_l2_intc_of_init()
181 		ret = -EINVAL;  in brcmstb_l2_intc_of_init()
185 	data->domain = irq_domain_add_linear(np, 32,  in brcmstb_l2_intc_of_init()
187 	if (!data->domain) {  in brcmstb_l2_intc_of_init()
188 		ret = -ENOMEM;  in brcmstb_l2_intc_of_init()
193 	 * peripheral registers for CPU-native byte order.  in brcmstb_l2_intc_of_init()
199 	if (init_params->handler == handle_level_irq)  in brcmstb_l2_intc_of_init()
203 	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,  in brcmstb_l2_intc_of_init()
204 			np->full_name, init_params->handler, clr, set, flags);  in brcmstb_l2_intc_of_init()
214 	data->gc = irq_get_domain_generic_chip(data->domain, 0);  in brcmstb_l2_intc_of_init()
215 	data->gc->reg_base = base;  in brcmstb_l2_intc_of_init()
216 	data->gc->private = data;  in brcmstb_l2_intc_of_init()
217 	data->status_offset = init_params->cpu_status;  in brcmstb_l2_intc_of_init()
218 	data->mask_offset = init_params->cpu_mask_status;  in brcmstb_l2_intc_of_init()
220 	ct = data->gc->chip_types;  in brcmstb_l2_intc_of_init()
222 	if (init_params->cpu_clear >= 0) {  in brcmstb_l2_intc_of_init()
223 		ct->regs.ack = init_params->cpu_clear;  in brcmstb_l2_intc_of_init()
224 		ct->chip.irq_ack = irq_gc_ack_set_bit;  in brcmstb_l2_intc_of_init()
225 		ct->chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set;  in brcmstb_l2_intc_of_init()
227 		/* No Ack - but still slightly more efficient to define this */  in brcmstb_l2_intc_of_init()
228 		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;  in brcmstb_l2_intc_of_init()
231 	ct->chip.irq_mask = irq_gc_mask_disable_reg;  in brcmstb_l2_intc_of_init()
232 	ct->regs.disable = init_params->cpu_mask_set;  in brcmstb_l2_intc_of_init()
233 	ct->regs.mask = init_params->cpu_mask_status;  in brcmstb_l2_intc_of_init()
235 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;  in brcmstb_l2_intc_of_init()
236 	ct->regs.enable = init_params->cpu_mask_clear;  in brcmstb_l2_intc_of_init()
238 	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;  in brcmstb_l2_intc_of_init()
239 	ct->chip.irq_resume = brcmstb_l2_intc_resume;  in brcmstb_l2_intc_of_init()
240 	ct->chip.irq_pm_shutdown = brcmstb_l2_intc_shutdown;  in brcmstb_l2_intc_of_init()
242 	if (data->can_wake) {  in brcmstb_l2_intc_of_init()
246 		data->gc->wake_enabled = 0xffffffff;  in brcmstb_l2_intc_of_init()
247 		ct->chip.irq_set_wake = irq_gc_set_wake;  in brcmstb_l2_intc_of_init()
251 	pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);  in brcmstb_l2_intc_of_init()
256 	irq_domain_remove(data->domain);  in brcmstb_l2_intc_of_init()
277 IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
278 IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
279 IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
280 IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
282 MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");