1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright © 2022-2024 Rivos Inc.
4  * Copyright © 2023 FORTH-ICS/CARV
14 #include <linux/iommu.h>
18 #include "iommu-bits.h"
26 	unsigned int mask;			/* index mask, queue length - 1 */
28 	struct riscv_iommu_device *iommu;	/* iommu device handling the queue when active */  member
29 	void *base;				/* ring buffer kernel pointer */  member
31 	u16 qbr;				/* base register offset, head and tail reference */
37 	/* iommu core interface */
38 	struct iommu_device iommu;  member
40 	/* iommu hardware */
65 int riscv_iommu_init(struct riscv_iommu_device *iommu);
66 void riscv_iommu_remove(struct riscv_iommu_device *iommu);
67 void riscv_iommu_disable(struct riscv_iommu_device *iommu);
69 #define riscv_iommu_readl(iommu, addr) \  argument
70 	readl_relaxed((iommu)->reg + (addr))
72 #define riscv_iommu_readq(iommu, addr) \  argument
73 	readq_relaxed((iommu)->reg + (addr))
75 #define riscv_iommu_writel(iommu, addr, val) \  argument
76 	writel_relaxed((val), (iommu)->reg + (addr))
78 #define riscv_iommu_writeq(iommu, addr, val) \  argument
79 	writeq_relaxed((val), (iommu)->reg + (addr))
81 #define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \  argument
82 	readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \
85 #define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \  argument
86 	readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \