Lines Matching +full:32 +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2024 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
9 * Based on the 'RISC-V IOMMU Architecture Specification', Version 1.0
10 * Published at https://github.com/riscv-non-isa/riscv-iommu
19 #include <linux/bits.h>
39 /* 5.3 IOMMU Capabilities (64bits) */
61 #define RISCV_IOMMU_CAPABILITIES_PAS GENMASK_ULL(37, 32)
67 * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings
69 * @RISCV_IOMMU_CAPABILITIES_IGS_WSI: IOMMU supports only Wired-Signaled interrupt
80 /* 5.4 Features control register (32bits) */
86 /* 5.5 Device-directory-table pointer (64bits) */
93 * enum riscv_iommu_ddtp_modes - IOMMU translation modes
95 * @RISCV_IOMMU_DDTP_IOMMU_MODE_BARE: Pass-through mode
96 * @RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL: One-level DDT
97 * @RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL: Two-level DDT
98 * @RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL: Three-level DDT
110 /* 5.6 Command Queue Base (64bits) */
115 /* 5.7 Command Queue head (32bits) */
119 /* 5.8 Command Queue tail (32bits) */
123 /* 5.9 Fault Queue Base (64bits) */
128 /* 5.10 Fault Queue Head (32bits) */
132 /* 5.11 Fault Queue tail (32bits) */
136 /* 5.12 Page Request Queue base (64bits) */
141 /* 5.13 Page Request Queue head (32bits) */
145 /* 5.14 Page Request Queue tail (32bits) */
149 /* 5.15 Command Queue CSR (32bits) */
160 /* 5.16 Fault Queue CSR (32bits) */
169 /* 5.17 Page Request Queue CSR (32bits) */
178 /* 5.18 Interrupt Pending Status (32bits) */
192 /* 5.19 Performance monitoring counter overflow status (32bits) */
197 /* 5.20 Performance monitoring counter inhibits (32bits) */
202 /* 5.21 Performance monitoring cycles counter (64bits) */
207 /* 5.22 Performance monitoring event counters (31 * 64bits) */
211 /* 5.23 Performance monitoring event selectors (31 * 64bits) */
223 /* Number of defined performance-monitoring event selectors */
227 * enum riscv_iommu_hpmevent_id - Performance-monitoring event identifier
236 * @RISCV_IOMMU_HPMEVENT_S_VS_WALKS: First-stage page table walks
237 * @RISCV_IOMMU_HPMEVENT_G_WALKS: Second-stage page table walks
253 /* 5.24 Translation request IOVA (64bits) */
257 /* 5.25 Translation request control (64bits) */
264 #define RISCV_IOMMU_TR_REQ_CTL_PV BIT_ULL(32)
267 /* 5.26 Translation request response (64bits) */
274 /* 5.27 Interrupt cause to vector (64bits) */
281 /* 5.28 MSI Configuration table (32 * 64bits) */
300 * Device Directory Table macros for non-leaf nodes
306 * struct riscv_iommu_dc - Device Context
348 /* Second-stage (aka G-stage) context fields */
354 * enum riscv_iommu_dc_iohgatp_modes - Guest address translation/protection modes
356 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4: Sv32x4 (2-bit extension of Sv32), when fctl.GXL == 1
357 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: Sv39x4 (2-bit extension of Sv39), when fctl.GXL == 0
358 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: Sv48x4 (2-bit extension of Sv48), when fctl.GXL == 0
359 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: Sv57x4 (2-bit extension of Sv57), when fctl.GXL == 0
372 /* First-stage context fields */
377 * enum riscv_iommu_dc_fsc_atp_modes - First stage address translation/protection modes
389 * the RISC-V MMU), and PDTP holds the process directory table, used to select a
417 * struct riscv_iommu_pc - Process Context
440 * Chapter 3: In-memory queue interface
444 * struct riscv_iommu_command - Generic IOMMU command structure
449 * 7bits of the first field are the opcode which also defines the
451 * function invoked by that command, and the rest is opcode-specific.
465 /* 3.1.1 IOMMU Page-table cache invalidation */
472 #define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32)
475 /* dword1[61:10] is the 4K-aligned page address */
486 #define RISCV_IOMMU_CMD_IOFENCE_DATA GENMASK_ULL(63, 32)
487 /* dword1 is the address, word-size aligned and shifted to the right by two bits. */
505 #define RISCV_IOMMU_CMD_ATS_PV BIT_ULL(32)
513 /* Bits 1 - 10 are zeroed */
518 /* Bits 0 - 31 are zeroed */
519 #define RISCV_IOMMU_CMD_ATS_PRGR_PRG_INDEX GENMASK_ULL(40, 32)
520 /* Bits 41 - 43 are zeroed */
525 * struct riscv_iommu_fq_record - Fault/Event Queue Record
527 * @_reserved: Low 32bits for custom use, high 32bits for standard use
528 * @iotval: Transaction-type/cause specific format
532 * processing transactions. Each record is a 32byte structure where
535 * fault/event-specific information. For more details see section
548 #define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32)
554 * enum riscv_iommu_fq_causes - Fault/event cause values
586 * Values are on table 11 of the spec, encodings 275 - 2047 are reserved for standard
587 * use, and 2048 - 4095 for custom use.
634 * Values are on table 12 of the spec, type 4 and 10 - 31 are reserved for standard use
635 * and 31 - 63 for custom use.
650 * struct riscv_iommu_pq_record - PCIe Page Request record
652 * @payload: Holds the page address, request group and permission bits
663 #define RISCV_IOMMU_PQ_HDR_PV BIT_ULL(32)
677 * struct riscv_iommu_msipte - MSI Page Table Entry
679 * @mrif_info: Memory-resident interrupt file info
685 * is an array of MSI PTEs, not a multi-level pt, each entry
689 * be used by software, any other reserved fields on pte must be zeroed-out
713 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | in riscv_iommu_cmd_inval_vma()
715 cmd->dword1 = 0; in riscv_iommu_cmd_inval_vma()
721 cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, phys_to_pfn(addr)); in riscv_iommu_cmd_inval_set_addr()
722 cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV; in riscv_iommu_cmd_inval_set_addr()
728 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_PSCID, pscid) | in riscv_iommu_cmd_inval_set_pscid()
735 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_GSCID, gscid) | in riscv_iommu_cmd_inval_set_gscid()
741 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence()
744 cmd->dword1 = 0; in riscv_iommu_cmd_iofence()
750 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence_set_av()
754 cmd->dword1 = addr >> 2; in riscv_iommu_cmd_iofence_set_av()
759 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_ddt()
761 cmd->dword1 = 0; in riscv_iommu_cmd_iodir_inval_ddt()
766 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_pdt()
768 cmd->dword1 = 0; in riscv_iommu_cmd_iodir_inval_pdt()
774 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_DID, devid) | in riscv_iommu_cmd_iodir_set_did()
781 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_PID, pasid); in riscv_iommu_cmd_iodir_set_pid()