1 // SPDX-License-Identifier: GPL-2.0
17 #include "iommu.h"
116 	struct intel_iommu *iommu;  in iommu_regset_show()  local
122 	for_each_active_iommu(iommu, drhd) {  in iommu_regset_show()
123 		if (!drhd->reg_base_addr) {  in iommu_regset_show()
124 			seq_puts(m, "IOMMU: Invalid base address\n");  in iommu_regset_show()
125 			ret = -EINVAL;  in iommu_regset_show()
129 		seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",  in iommu_regset_show()
130 			   iommu->name, drhd->reg_base_addr);  in iommu_regset_show()
133 		 * Publish the contents of the 64-bit hardware registers  in iommu_regset_show()
136 		raw_spin_lock_irqsave(&iommu->register_lock, flag);  in iommu_regset_show()
138 			value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);  in iommu_regset_show()
139 			seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",  in iommu_regset_show()
144 			value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);  in iommu_regset_show()
145 			seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",  in iommu_regset_show()
149 		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in iommu_regset_show()
161 	struct tbl_walk *tbl_wlk = m->private;  in print_tbl_walk()
164 		   tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),  in print_tbl_walk()
165 		   PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,  in print_tbl_walk()
166 		   tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,  in print_tbl_walk()
167 		   tbl_wlk->ctx_entry->lo);  in print_tbl_walk()
170 	 * A legacy mode DMAR doesn't support PASID, hence default it to -1  in print_tbl_walk()
174 	if (!tbl_wlk->pasid_tbl_entry)  in print_tbl_walk()
175 		seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,  in print_tbl_walk()
178 		seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",  in print_tbl_walk()
179 			   tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],  in print_tbl_walk()
180 			   tbl_wlk->pasid_tbl_entry->val[1],  in print_tbl_walk()
181 			   tbl_wlk->pasid_tbl_entry->val[0]);  in print_tbl_walk()
187 	struct tbl_walk *tbl_wlk = m->private;  in pasid_tbl_walk()
192 			tbl_wlk->pasid_tbl_entry = tbl_entry;  in pasid_tbl_walk()
193 			tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;  in pasid_tbl_walk()
217 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)  in ctx_tbl_walk()  argument
239 		context = iommu_context_addr(iommu, bus, devfn, 0);  in ctx_tbl_walk()
248 		tbl_wlk.rt_entry = &iommu->root_entry[bus];  in ctx_tbl_walk()
250 		m->private = &tbl_wlk;  in ctx_tbl_walk()
252 		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {  in ctx_tbl_walk()
253 			pasid_dir_ptr = context->lo & VTD_PAGE_MASK;  in ctx_tbl_walk()
263 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)  in root_tbl_walk()  argument
267 	spin_lock(&iommu->lock);  in root_tbl_walk()
268 	seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,  in root_tbl_walk()
269 		   (u64)virt_to_phys(iommu->root_entry));  in root_tbl_walk()
278 		ctx_tbl_walk(m, iommu, bus);  in root_tbl_walk()
279 	spin_unlock(&iommu->lock);  in root_tbl_walk()
285 	struct intel_iommu *iommu;  in dmar_translation_struct_show()  local
289 	for_each_active_iommu(iommu, drhd) {  in dmar_translation_struct_show()
290 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in dmar_translation_struct_show()
293 				   iommu->name);  in dmar_translation_struct_show()
296 		root_tbl_walk(m, iommu);  in dmar_translation_struct_show()
307 	return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));  in level_to_directory_size()
337 		path[level] = pde->val;  in pgtable_walk_level()
342 					   level - 1, start, path);  in pgtable_walk_level()
353 	struct intel_iommu *iommu;  in domain_translation_struct_show()  local
356 	bus = info->bus;  in domain_translation_struct_show()
357 	devfn = info->devfn;  in domain_translation_struct_show()
358 	seg = info->segment;  in domain_translation_struct_show()
361 	for_each_active_iommu(iommu, drhd) {  in domain_translation_struct_show()
366 		if (seg != iommu->segment)  in domain_translation_struct_show()
369 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in domain_translation_struct_show()
372 				   iommu->name);  in domain_translation_struct_show()
375 		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)  in domain_translation_struct_show()
381 		 * The iommu->lock is held across the callback, which will  in domain_translation_struct_show()
386 		 * interface. This could be solved by RCU-freeing the page  in domain_translation_struct_show()
389 		spin_lock(&iommu->lock);  in domain_translation_struct_show()
391 		context = iommu_context_addr(iommu, bus, devfn, 0);  in domain_translation_struct_show()
401 			pasid_dir_ptr = context->lo & VTD_PAGE_MASK;  in domain_translation_struct_show()
422 			pgtt = (u16)(pasid_tbl_entry->val[0] & GENMASK_ULL(8, 6)) >> 6;  in domain_translation_struct_show()
423 			agaw = (u8)(pasid_tbl_entry->val[0] & GENMASK_ULL(4, 2)) >> 2;  in domain_translation_struct_show()
427 				pgd = pasid_tbl_entry->val[2];  in domain_translation_struct_show()
431 				pgd = pasid_tbl_entry->val[0];  in domain_translation_struct_show()
438 			pgd = context->lo & VTD_PAGE_MASK;  in domain_translation_struct_show()
439 			agaw = context->hi & 7;  in domain_translation_struct_show()
443 			   iommu->segment, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));  in domain_translation_struct_show()
450 		seq_printf(m, "%-17s\t%-18s\t%-18s\t%-18s\t%-18s\t%-s\n",  in domain_translation_struct_show()
456 		spin_unlock(&iommu->lock);  in domain_translation_struct_show()
467 	struct device_domain_info *info = (struct device_domain_info *)m->private;  in dev_domain_translation_struct_show()
475 	struct dev_pasid_info *dev_pasid = (struct dev_pasid_info *)m->private;  in pasid_domain_translation_struct_show()
476 	struct device_domain_info *info = dev_iommu_priv_get(dev_pasid->dev);  in pasid_domain_translation_struct_show()
478 	return domain_translation_struct_show(m, info, dev_pasid->pasid);  in pasid_domain_translation_struct_show()
483 					  struct intel_iommu *iommu)  in invalidation_queue_entry_show()  argument
485 	int index, shift = qi_shift(iommu);  in invalidation_queue_entry_show()
489 	if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
496 		desc = iommu->qi->desc + offset;  in invalidation_queue_entry_show()
497 		if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
499 				   index, desc->qw0, desc->qw1,  in invalidation_queue_entry_show()
500 				   desc->qw2, desc->qw3,  in invalidation_queue_entry_show()
501 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
504 				   index, desc->qw0, desc->qw1,  in invalidation_queue_entry_show()
505 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
512 	struct intel_iommu *iommu;  in invalidation_queue_show()  local
518 	for_each_active_iommu(iommu, drhd) {  in invalidation_queue_show()
519 		qi = iommu->qi;  in invalidation_queue_show()
520 		shift = qi_shift(iommu);  in invalidation_queue_show()
522 		if (!qi || !ecap_qis(iommu->ecap))  in invalidation_queue_show()
525 		seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);  in invalidation_queue_show()
527 		raw_spin_lock_irqsave(&qi->q_lock, flags);  in invalidation_queue_show()
528 		seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",  in invalidation_queue_show()
529 			   (u64)virt_to_phys(qi->desc),  in invalidation_queue_show()
530 			   dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,  in invalidation_queue_show()
531 			   dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);  in invalidation_queue_show()
532 		invalidation_queue_entry_show(m, iommu);  in invalidation_queue_show()
533 		raw_spin_unlock_irqrestore(&qi->q_lock, flags);  in invalidation_queue_show()
544 				    struct intel_iommu *iommu)  in ir_tbl_remap_entry_show()  argument
554 		ri_entry = &iommu->ir_table->base[idx];  in ir_tbl_remap_entry_show()
555 		if (!ri_entry->present || ri_entry->p_pst)  in ir_tbl_remap_entry_show()
558 		seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x  %016llx\t%016llx\n",  in ir_tbl_remap_entry_show()
559 			   idx, PCI_BUS_NUM(ri_entry->sid),  in ir_tbl_remap_entry_show()
560 			   PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),  in ir_tbl_remap_entry_show()
561 			   ri_entry->dest_id, ri_entry->vector,  in ir_tbl_remap_entry_show()
562 			   ri_entry->high, ri_entry->low);  in ir_tbl_remap_entry_show()
568 				     struct intel_iommu *iommu)  in ir_tbl_posted_entry_show()  argument
578 		pi_entry = &iommu->ir_table->base[idx];  in ir_tbl_posted_entry_show()
579 		if (!pi_entry->present || !pi_entry->p_pst)  in ir_tbl_posted_entry_show()
582 		seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x  %016llx\t%016llx\n",  in ir_tbl_posted_entry_show()
583 			   idx, PCI_BUS_NUM(pi_entry->sid),  in ir_tbl_posted_entry_show()
584 			   PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),  in ir_tbl_posted_entry_show()
585 			   pi_entry->pda_h, pi_entry->pda_l << 6,  in ir_tbl_posted_entry_show()
586 			   pi_entry->vector, pi_entry->high,  in ir_tbl_posted_entry_show()
587 			   pi_entry->low);  in ir_tbl_posted_entry_show()
600 	struct intel_iommu *iommu;  in ir_translation_struct_show()  local
605 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
606 		if (!ecap_ir_support(iommu->ecap))  in ir_translation_struct_show()
609 		seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",  in ir_translation_struct_show()
610 			   iommu->name);  in ir_translation_struct_show()
612 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in ir_translation_struct_show()
613 		if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {  in ir_translation_struct_show()
614 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
616 			ir_tbl_remap_entry_show(m, iommu);  in ir_translation_struct_show()
625 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
626 		if (!cap_pi_support(iommu->cap))  in ir_translation_struct_show()
629 		seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",  in ir_translation_struct_show()
630 			   iommu->name);  in ir_translation_struct_show()
632 		if (iommu->ir_table) {  in ir_translation_struct_show()
633 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
635 			ir_tbl_posted_entry_show(m, iommu);  in ir_translation_struct_show()
648 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,  in latency_show_one()  argument
653 	seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",  in latency_show_one()
654 		   iommu->name, drhd->reg_base_addr);  in latency_show_one()
656 	ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);  in latency_show_one()
667 	struct intel_iommu *iommu;  in latency_show()  local
670 	for_each_active_iommu(iommu, drhd)  in latency_show()
671 		latency_show_one(m, iommu, drhd);  in latency_show()
687 	struct intel_iommu *iommu;  in dmar_perf_latency_write()  local
695 		return -EFAULT;  in dmar_perf_latency_write()
700 		return -EINVAL;  in dmar_perf_latency_write()
705 		for_each_active_iommu(iommu, drhd) {  in dmar_perf_latency_write()
706 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
707 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
708 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
714 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
715 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
720 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
721 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
726 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
727 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
731 		return -EINVAL;  in dmar_perf_latency_write()
768  * /sys/kernel/debug/iommu/intel/0000:00:01.0/domain_translation_struct
772 	info->debugfs_dentry = debugfs_create_dir(dev_name(info->dev), intel_iommu_debug);  in intel_iommu_debugfs_create_dev()
774 	debugfs_create_file("domain_translation_struct", 0444, info->debugfs_dentry,  in intel_iommu_debugfs_create_dev()
781 	debugfs_remove_recursive(info->debugfs_dentry);  in intel_iommu_debugfs_remove_dev()
788  * /sys/kernel/debug/iommu/intel/0000:00:01.0/1/domain_translation_struct
796 	struct device_domain_info *info = dev_iommu_priv_get(dev_pasid->dev);  in intel_iommu_debugfs_create_dev_pasid()
799 	sprintf(dir_name, "%x", dev_pasid->pasid);  in intel_iommu_debugfs_create_dev_pasid()
800 	dev_pasid->debugfs_dentry = debugfs_create_dir(dir_name, info->debugfs_dentry);  in intel_iommu_debugfs_create_dev_pasid()
802 	debugfs_create_file("domain_translation_struct", 0444, dev_pasid->debugfs_dentry,  in intel_iommu_debugfs_create_dev_pasid()
809 	debugfs_remove_recursive(dev_pasid->debugfs_dentry);  in intel_iommu_debugfs_remove_dev_pasid()