21 #define OMI_QMAN        0x00
22 #define OMI_FMAN        0x01
23 #define OMI_QMAN_PRIV   0x02
24 #define OMI_CAAM        0x03
90  * Returns 0 upon success else error code < 0 returned
113 	return 0;  in pamu_enable_liodn()
120  * Returns 0 upon success else error code < 0 returned
135 	return 0;  in pamu_disable_liodn()
177 	return 0;  in pamu_update_paace_stash()
184  * @omi: Operation mapping index -- if ~omi == 0 then omi not defined
185  * @stashid: cache stash id for associated cpu -- if ~stashid == 0 then
189  * Returns 0 upon success else error code < 0 returned
205 	ppaace->wbah = 0;  in pamu_config_ppaace()
206 	set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, 0);  in pamu_config_ppaace()
212 	} else if (~omi != 0) {  in pamu_config_ppaace()
218 	if (~stashid != 0)  in pamu_config_ppaace()
222 	ppaace->twbah = 0;  in pamu_config_ppaace()
223 	set_bf(ppaace->win_bitfields, PAACE_WIN_TWBAL, 0);  in pamu_config_ppaace()
225 	set_bf(ppaace->impl_attr, PAACE_IA_WCE, 0);  in pamu_config_ppaace()
226 	set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);  in pamu_config_ppaace()
229 	return 0;  in pamu_config_ppaace()
253  * Returs stash on success or ~(u32)0 on failure.
261 	int len, found = 0;  in get_stash_id()
273 				return ~(u32)0;  in get_stash_id()
278 		return ~(u32)0;  in get_stash_id()
283 		for (i = 0; i < len / sizeof(u32); i++) {  in get_stash_id()
300 				return ~(u32)0;  in get_stash_id()
310 			return ~(u32)0;  /* can't traverse any further */  in get_stash_id()
318 			return ~(u32)0;  in get_stash_id()
324 	return ~(u32)0;  in get_stash_id()
344 		set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));  in setup_qbman_paace()
346 		       0);  in setup_qbman_paace()
352 		set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));  in setup_qbman_paace()
356 		       0);  in setup_qbman_paace()
454 	return 0;  in setup_one_pamu()
467 		for (i = 0; i < len / sizeof(u32); i++) {  in setup_liodns()
479 			ppaace->wbah = 0;  in setup_liodns()
480 			set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, 0);  in setup_liodns()
505 	for (i = 0; i < data->count; i++) {  in pamu_av_isr()
533 				for (j = 0; j < 4; j++)  in pamu_av_isr()
565 #define LAWAR_EN		0x80000000
566 #define LAWAR_TARGET_MASK	0x0FF00000
568 #define LAWAR_SIZE_MASK		0x0000003F
569 #define LAWAR_CSDID_MASK	0x000FF000
572 #define LAW_SIZE_4K		0xb
593 	u32 law_target = 0;  in create_csd()
594 	u32 csd_id = 0;  in create_csd()
595 	int ret = 0;  in create_csd()
613 	lac = of_iomap(np, 0);  in create_csd()
619 	/* LAW registers are at offset 0xC00 */  in create_csd()
620 	law = lac + 0xC00;  in create_csd()
642 	ccm = of_iomap(np, 0);  in create_csd()
648 	/* The undocumented CSDID registers are at offset 0x600 */  in create_csd()
649 	csdids = ccm + 0x600;  in create_csd()
655 	for (csd_id = 0; csd_id < num_csds; csd_id++) {  in create_csd()
664 	for (i = 0; i < num_laws; i++) {  in create_csd()
679 	if (i == 0 || i == num_laws) {  in create_csd()
687 		if (i == 0) {  in create_csd()
727 	{(SVR_P2040 << 8) | 0x10, 0xFF000000},	/* P2040 1.0 */
728 	{(SVR_P2040 << 8) | 0x11, 0xFF000000},	/* P2040 1.1 */
729 	{(SVR_P2041 << 8) | 0x10, 0xFF000000},	/* P2041 1.0 */
730 	{(SVR_P2041 << 8) | 0x11, 0xFF000000},	/* P2041 1.1 */
731 	{(SVR_P3041 << 8) | 0x10, 0xFF000000},	/* P3041 1.0 */
732 	{(SVR_P3041 << 8) | 0x11, 0xFF000000},	/* P3041 1.1 */
733 	{(SVR_P4040 << 8) | 0x20, 0xFFF80000},	/* P4040 2.0 */
734 	{(SVR_P4080 << 8) | 0x20, 0xFFF80000},	/* P4080 2.0 */
735 	{(SVR_P5010 << 8) | 0x10, 0xFC000000},	/* P5010 1.0 */
736 	{(SVR_P5010 << 8) | 0x20, 0xFC000000},	/* P5010 2.0 */
737 	{(SVR_P5020 << 8) | 0x10, 0xFC000000},	/* P5020 1.0 */
738 	{(SVR_P5021 << 8) | 0x10, 0xFF800000},	/* P5021 1.0 */
739 	{(SVR_P5040 << 8) | 0x10, 0xFF800000},	/* P5040 1.0 */
742 #define SVR_SECURITY	0x80000	/* The Security (E) bit */
756 	int ret = 0;  in fsl_pamu_probe()
762 	size_t mem_size = 0;  in fsl_pamu_probe()
763 	unsigned int order = 0;  in fsl_pamu_probe()
764 	u32 csd_port_id = 0;  in fsl_pamu_probe()
775 	pamu_regs = of_iomap(dev->of_node, 0);  in fsl_pamu_probe()
780 	of_get_address(dev->of_node, 0, &size, NULL);  in fsl_pamu_probe()
782 	irq = irq_of_parse_and_map(dev->of_node, 0);  in fsl_pamu_probe()
797 	ret = request_irq(irq, pamu_av_isr, 0, "pamu", data);  in fsl_pamu_probe()
798 	if (ret < 0) {  in fsl_pamu_probe()
810 	guts_regs = of_iomap(guts_node, 0);  in fsl_pamu_probe()
856 	for (i = 0; i < ARRAY_SIZE(port_id_map); i++) {  in fsl_pamu_probe()
866 		dev_dbg(dev, "creating coherency subdomain at address %pa, size %zu, port id 0x%08x",  in fsl_pamu_probe()
881 	for (pamu_reg_off = 0, pamu_counter = 0x80000000; pamu_reg_off < size;  in fsl_pamu_probe()
904 	return 0;  in fsl_pamu_probe()
970 	pdev = platform_device_alloc("fsl-of-pamu", 0);  in fsl_pamu_init()
988 	return 0;  in fsl_pamu_init()