3  * IOMMU API for ARM architected SMMU implementations.
254 /* Maximum number of context banks per SMMU */
379 	struct arm_smmu_device		*smmu;  member
385 	struct mutex			init_mutex; /* Protects smmu pointer */
391 	struct arm_smmu_device		*smmu;  member
436 	u32 (*read_reg)(struct arm_smmu_device *smmu, int page, int offset);
437 	void (*write_reg)(struct arm_smmu_device *smmu, int page, int offset,
439 	u64 (*read_reg64)(struct arm_smmu_device *smmu, int page, int offset);
440 	void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset,
442 	int (*cfg_probe)(struct arm_smmu_device *smmu);
443 	int (*reset)(struct arm_smmu_device *smmu);
446 	void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync,
453 				  struct arm_smmu_device *smmu,
455 	void (*write_s2cr)(struct arm_smmu_device *smmu, int idx);
456 	void (*write_sctlr)(struct arm_smmu_device *smmu, int idx, u32 reg);
457 	void (*probe_finalize)(struct arm_smmu_device *smmu, struct device *dev);
479 static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)  in arm_smmu_page()  argument
481 	return smmu->base + (n << smmu->pgshift);  in arm_smmu_page()
484 static inline u32 arm_smmu_readl(struct arm_smmu_device *smmu, int page, int offset)  in arm_smmu_readl()  argument
486 	if (smmu->impl && unlikely(smmu->impl->read_reg))  in arm_smmu_readl()
487 		return smmu->impl->read_reg(smmu, page, offset);  in arm_smmu_readl()
488 	return readl_relaxed(arm_smmu_page(smmu, page) + offset);  in arm_smmu_readl()
491 static inline void arm_smmu_writel(struct arm_smmu_device *smmu, int page,  in arm_smmu_writel()  argument
494 	if (smmu->impl && unlikely(smmu->impl->write_reg))  in arm_smmu_writel()
495 		smmu->impl->write_reg(smmu, page, offset, val);  in arm_smmu_writel()
497 		writel_relaxed(val, arm_smmu_page(smmu, page) + offset);  in arm_smmu_writel()
500 static inline u64 arm_smmu_readq(struct arm_smmu_device *smmu, int page, int offset)  in arm_smmu_readq()  argument
502 	if (smmu->impl && unlikely(smmu->impl->read_reg64))  in arm_smmu_readq()
503 		return smmu->impl->read_reg64(smmu, page, offset);  in arm_smmu_readq()
504 	return readq_relaxed(arm_smmu_page(smmu, page) + offset);  in arm_smmu_readq()
507 static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,  in arm_smmu_writeq()  argument
510 	if (smmu->impl && unlikely(smmu->impl->write_reg64))  in arm_smmu_writeq()
511 		smmu->impl->write_reg64(smmu, page, offset, val);  in arm_smmu_writeq()
513 		writeq_relaxed(val, arm_smmu_page(smmu, page) + offset);  in arm_smmu_writeq()
539 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
540 struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu);
541 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
543 void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
544 int arm_mmu500_reset(struct arm_smmu_device *smmu);
553 void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
556 void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,