Lines Matching +full:arm +full:- +full:smmu
1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for ARM architected SMMU implementations.
5 * Copyright (C) 2013 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-mapping.h>
41 #include "arm-smmu.h"
42 #include "../../dma-iommu.h"
45 * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
51 #define QCOM_DUMMY_VAL -1
59 …"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' f…
64 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
72 static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) in arm_smmu_rpm_get() argument
74 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_get()
75 return pm_runtime_resume_and_get(smmu->dev); in arm_smmu_rpm_get()
80 static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) in arm_smmu_rpm_put() argument
82 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_put()
83 pm_runtime_put_autosuspend(smmu->dev); in arm_smmu_rpm_put()
86 static void arm_smmu_rpm_use_autosuspend(struct arm_smmu_device *smmu) in arm_smmu_rpm_use_autosuspend() argument
96 * to 5-10sec worth of reprogramming the context bank, while in arm_smmu_rpm_use_autosuspend()
99 pm_runtime_set_autosuspend_delay(smmu->dev, 20); in arm_smmu_rpm_use_autosuspend()
100 pm_runtime_use_autosuspend(smmu->dev); in arm_smmu_rpm_use_autosuspend()
115 struct pci_bus *bus = to_pci_dev(dev)->bus; in dev_get_dev_node()
118 bus = bus->parent; in dev_get_dev_node()
119 return of_node_get(bus->bridge->parent->of_node); in dev_get_dev_node()
122 return of_node_get(dev->of_node); in dev_get_dev_node()
134 struct device_node *np = it->node; in __find_legacy_master_phandle()
137 of_for_each_phandle(it, err, dev->of_node, "mmu-masters", in __find_legacy_master_phandle()
138 "#stream-id-cells", -1) in __find_legacy_master_phandle()
139 if (it->node == np) { in __find_legacy_master_phandle()
143 it->node = np; in __find_legacy_master_phandle()
144 return err == -ENOENT ? 0 : err; in __find_legacy_master_phandle()
148 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
159 if (!np || !of_property_present(np, "#stream-id-cells")) { in arm_smmu_register_legacy_master()
161 return -ENODEV; in arm_smmu_register_legacy_master()
170 return -ENODEV; in arm_smmu_register_legacy_master()
175 /* "mmu-masters" assumes Stream ID == Requester ID */ in arm_smmu_register_legacy_master()
188 return -ENOMEM; in arm_smmu_register_legacy_master()
190 *smmu = dev_get_drvdata(smmu_dev); in arm_smmu_register_legacy_master()
198 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
200 return -ENODEV; in arm_smmu_register_legacy_master()
210 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in __arm_smmu_tlb_sync() argument
216 if (smmu->impl && unlikely(smmu->impl->tlb_sync)) in __arm_smmu_tlb_sync()
217 return smmu->impl->tlb_sync(smmu, page, sync, status); in __arm_smmu_tlb_sync()
219 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in __arm_smmu_tlb_sync()
221 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in __arm_smmu_tlb_sync()
222 reg = arm_smmu_readl(smmu, page, status); in __arm_smmu_tlb_sync()
229 dev_err_ratelimited(smmu->dev, in __arm_smmu_tlb_sync()
230 "TLB sync timed out -- SMMU may be deadlocked\n"); in __arm_smmu_tlb_sync()
233 static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu) in arm_smmu_tlb_sync_global() argument
237 spin_lock_irqsave(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
238 __arm_smmu_tlb_sync(smmu, ARM_SMMU_GR0, ARM_SMMU_GR0_sTLBGSYNC, in arm_smmu_tlb_sync_global()
240 spin_unlock_irqrestore(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
245 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_sync_context() local
248 spin_lock_irqsave(&smmu_domain->cb_lock, flags); in arm_smmu_tlb_sync_context()
249 __arm_smmu_tlb_sync(smmu, ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx), in arm_smmu_tlb_sync_context()
251 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); in arm_smmu_tlb_sync_context()
262 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
263 ARM_SMMU_CB_S1_TLBIASID, smmu_domain->cfg.asid); in arm_smmu_tlb_inv_context_s1()
270 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context_s2() local
274 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_inv_context_s2()
275 arm_smmu_tlb_sync_global(smmu); in arm_smmu_tlb_inv_context_s2()
282 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s1() local
283 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_tlb_inv_range_s1()
284 int idx = cfg->cbndx; in arm_smmu_tlb_inv_range_s1()
286 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s1()
289 if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) { in arm_smmu_tlb_inv_range_s1()
291 iova |= cfg->asid; in arm_smmu_tlb_inv_range_s1()
293 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
295 } while (size -= granule); in arm_smmu_tlb_inv_range_s1()
298 iova |= (u64)cfg->asid << 48; in arm_smmu_tlb_inv_range_s1()
300 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
302 } while (size -= granule); in arm_smmu_tlb_inv_range_s1()
310 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s2() local
311 int idx = smmu_domain->cfg.cbndx; in arm_smmu_tlb_inv_range_s2()
313 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s2()
318 if (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_tlb_inv_range_s2()
319 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
321 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
323 } while (size -= granule); in arm_smmu_tlb_inv_range_s2()
330 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_tlb_inv_walk_s1()
332 if (cfg->flush_walk_prefer_tlbiasid) { in arm_smmu_tlb_inv_walk_s1()
371 * On MMU-401 at least, the cost of firing off multiple TLBIVMIDs appears
374 * no-op and call arm_smmu_tlb_inv_context_s2() from .iotlb_sync as you might
382 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_add_page_s2_v1() local
384 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_add_page_s2_v1()
387 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_add_page_s2_v1()
409 void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx, in arm_smmu_read_context_fault_info() argument
412 cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); in arm_smmu_read_context_fault_info()
413 cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); in arm_smmu_read_context_fault_info()
414 cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); in arm_smmu_read_context_fault_info()
415 cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); in arm_smmu_read_context_fault_info()
418 void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx, in arm_smmu_print_context_fault_info() argument
421 dev_err(smmu->dev, in arm_smmu_print_context_fault_info()
423 cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx); in arm_smmu_print_context_fault_info()
425 dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n", in arm_smmu_print_context_fault_info()
426 cfi->fsr, in arm_smmu_print_context_fault_info()
427 (cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "", in arm_smmu_print_context_fault_info()
428 (cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "", in arm_smmu_print_context_fault_info()
429 (u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr), in arm_smmu_print_context_fault_info()
430 (cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "", in arm_smmu_print_context_fault_info()
431 (cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "", in arm_smmu_print_context_fault_info()
432 (cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "", in arm_smmu_print_context_fault_info()
433 (cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "", in arm_smmu_print_context_fault_info()
434 (cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "", in arm_smmu_print_context_fault_info()
435 (cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "", in arm_smmu_print_context_fault_info()
436 (cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "", in arm_smmu_print_context_fault_info()
437 (cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "", in arm_smmu_print_context_fault_info()
438 cfi->cbfrsynra); in arm_smmu_print_context_fault_info()
440 dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n", in arm_smmu_print_context_fault_info()
441 cfi->fsynr, in arm_smmu_print_context_fault_info()
442 (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr), in arm_smmu_print_context_fault_info()
443 (cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "", in arm_smmu_print_context_fault_info()
444 (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "", in arm_smmu_print_context_fault_info()
445 (cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "", in arm_smmu_print_context_fault_info()
446 (cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "", in arm_smmu_print_context_fault_info()
447 (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "", in arm_smmu_print_context_fault_info()
448 (cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "", in arm_smmu_print_context_fault_info()
449 (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr)); in arm_smmu_print_context_fault_info()
456 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_context_fault() local
459 int idx = smmu_domain->cfg.cbndx; in arm_smmu_context_fault()
462 arm_smmu_read_context_fault_info(smmu, idx, &cfi); in arm_smmu_context_fault()
467 ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, in arm_smmu_context_fault()
470 if (ret == -ENOSYS && __ratelimit(&rs)) in arm_smmu_context_fault()
471 arm_smmu_print_context_fault_info(smmu, idx, &cfi); in arm_smmu_context_fault()
473 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); in arm_smmu_context_fault()
480 struct arm_smmu_device *smmu = dev; in arm_smmu_global_fault() local
484 gfsr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
485 gfsynr0 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); in arm_smmu_global_fault()
486 gfsynr1 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); in arm_smmu_global_fault()
487 gfsynr2 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); in arm_smmu_global_fault()
495 dev_err(smmu->dev, in arm_smmu_global_fault()
496 …"Blocked unknown Stream ID 0x%hx; boot with \"arm-smmu.disable_bypass=0\" to allow, but this may h… in arm_smmu_global_fault()
499 dev_err(smmu->dev, in arm_smmu_global_fault()
501 dev_err(smmu->dev, in arm_smmu_global_fault()
506 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); in arm_smmu_global_fault()
513 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_init_context_bank()
514 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in arm_smmu_init_context_bank()
515 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_init_context_bank()
517 cb->cfg = cfg; in arm_smmu_init_context_bank()
521 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_init_context_bank()
522 cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr; in arm_smmu_init_context_bank()
524 cb->tcr[0] = arm_smmu_lpae_tcr(pgtbl_cfg); in arm_smmu_init_context_bank()
525 cb->tcr[1] = arm_smmu_lpae_tcr2(pgtbl_cfg); in arm_smmu_init_context_bank()
526 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_init_context_bank()
527 cb->tcr[1] |= ARM_SMMU_TCR2_AS; in arm_smmu_init_context_bank()
529 cb->tcr[0] |= ARM_SMMU_TCR_EAE; in arm_smmu_init_context_bank()
532 cb->tcr[0] = arm_smmu_lpae_vtcr(pgtbl_cfg); in arm_smmu_init_context_bank()
537 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_init_context_bank()
538 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
539 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
541 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
542 cfg->asid); in arm_smmu_init_context_bank()
543 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
544 cfg->asid); in arm_smmu_init_context_bank()
546 if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) in arm_smmu_init_context_bank()
547 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
549 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
552 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
555 /* MAIRs (stage-1 only) */ in arm_smmu_init_context_bank()
557 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_init_context_bank()
558 cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr; in arm_smmu_init_context_bank()
559 cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr; in arm_smmu_init_context_bank()
561 cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair; in arm_smmu_init_context_bank()
562 cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32; in arm_smmu_init_context_bank()
567 void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_context_bank() argument
571 struct arm_smmu_cb *cb = &smmu->cbs[idx]; in arm_smmu_write_context_bank()
572 struct arm_smmu_cfg *cfg = cb->cfg; in arm_smmu_write_context_bank()
576 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
580 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_write_context_bank()
583 if (smmu->version > ARM_SMMU_V1) { in arm_smmu_write_context_bank()
584 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_write_context_bank()
588 /* 16-bit VMIDs live in CBA2R */ in arm_smmu_write_context_bank()
589 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_write_context_bank()
590 reg |= FIELD_PREP(ARM_SMMU_CBA2R_VMID16, cfg->vmid); in arm_smmu_write_context_bank()
592 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBA2R(idx), reg); in arm_smmu_write_context_bank()
596 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, cfg->cbar); in arm_smmu_write_context_bank()
597 if (smmu->version < ARM_SMMU_V2) in arm_smmu_write_context_bank()
598 reg |= FIELD_PREP(ARM_SMMU_CBAR_IRPTNDX, cfg->irptndx); in arm_smmu_write_context_bank()
609 } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { in arm_smmu_write_context_bank()
610 /* 8-bit VMIDs live in CBAR */ in arm_smmu_write_context_bank()
611 reg |= FIELD_PREP(ARM_SMMU_CBAR_VMID, cfg->vmid); in arm_smmu_write_context_bank()
613 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(idx), reg); in arm_smmu_write_context_bank()
620 if (stage1 && smmu->version > ARM_SMMU_V1) in arm_smmu_write_context_bank()
621 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
622 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
625 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_write_context_bank()
626 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_CONTEXTIDR, cfg->asid); in arm_smmu_write_context_bank()
627 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
628 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
630 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
632 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR1, in arm_smmu_write_context_bank()
633 cb->ttbr[1]); in arm_smmu_write_context_bank()
636 /* MAIRs (stage-1 only) */ in arm_smmu_write_context_bank()
638 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR0, cb->mair[0]); in arm_smmu_write_context_bank()
639 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR1, cb->mair[1]); in arm_smmu_write_context_bank()
650 if (smmu->impl && smmu->impl->write_sctlr) in arm_smmu_write_context_bank()
651 smmu->impl->write_sctlr(smmu, idx, reg); in arm_smmu_write_context_bank()
653 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
657 struct arm_smmu_device *smmu, in arm_smmu_alloc_context_bank() argument
660 if (smmu->impl && smmu->impl->alloc_context_bank) in arm_smmu_alloc_context_bank()
661 return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_alloc_context_bank()
663 return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); in arm_smmu_alloc_context_bank()
667 struct arm_smmu_device *smmu, in arm_smmu_init_domain_context() argument
675 struct iommu_domain *domain = &smmu_domain->domain; in arm_smmu_init_domain_context()
676 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_init_domain_context()
679 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_init_domain_context()
680 if (smmu_domain->smmu) in arm_smmu_init_domain_context()
699 * Note that you can't actually request stage-2 mappings. in arm_smmu_init_domain_context()
701 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_init_domain_context()
702 smmu_domain->stage = ARM_SMMU_DOMAIN_S2; in arm_smmu_init_domain_context()
703 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_init_domain_context()
704 smmu_domain->stage = ARM_SMMU_DOMAIN_S1; in arm_smmu_init_domain_context()
709 * the decision into the io-pgtable code where it arguably belongs, in arm_smmu_init_domain_context()
714 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) in arm_smmu_init_domain_context()
715 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L; in arm_smmu_init_domain_context()
718 (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && in arm_smmu_init_domain_context()
719 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)) in arm_smmu_init_domain_context()
720 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_S; in arm_smmu_init_domain_context()
721 if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) && in arm_smmu_init_domain_context()
722 (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | in arm_smmu_init_domain_context()
725 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64; in arm_smmu_init_domain_context()
727 if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) { in arm_smmu_init_domain_context()
728 ret = -EINVAL; in arm_smmu_init_domain_context()
732 switch (smmu_domain->stage) { in arm_smmu_init_domain_context()
734 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; in arm_smmu_init_domain_context()
735 start = smmu->num_s2_context_banks; in arm_smmu_init_domain_context()
736 ias = smmu->va_size; in arm_smmu_init_domain_context()
737 oas = smmu->ipa_size; in arm_smmu_init_domain_context()
738 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { in arm_smmu_init_domain_context()
740 } else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) { in arm_smmu_init_domain_context()
749 smmu_domain->flush_ops = &arm_smmu_s1_tlb_ops; in arm_smmu_init_domain_context()
757 cfg->cbar = CBAR_TYPE_S2_TRANS; in arm_smmu_init_domain_context()
759 ias = smmu->ipa_size; in arm_smmu_init_domain_context()
760 oas = smmu->pa_size; in arm_smmu_init_domain_context()
761 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { in arm_smmu_init_domain_context()
768 if (smmu->version == ARM_SMMU_V2) in arm_smmu_init_domain_context()
769 smmu_domain->flush_ops = &arm_smmu_s2_tlb_ops_v2; in arm_smmu_init_domain_context()
771 smmu_domain->flush_ops = &arm_smmu_s2_tlb_ops_v1; in arm_smmu_init_domain_context()
774 ret = -EINVAL; in arm_smmu_init_domain_context()
778 ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_init_domain_context()
783 smmu_domain->smmu = smmu; in arm_smmu_init_domain_context()
785 cfg->cbndx = ret; in arm_smmu_init_domain_context()
786 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_init_domain_context()
787 cfg->irptndx = atomic_inc_return(&smmu->irptndx); in arm_smmu_init_domain_context()
788 cfg->irptndx %= smmu->num_context_irqs; in arm_smmu_init_domain_context()
790 cfg->irptndx = cfg->cbndx; in arm_smmu_init_domain_context()
793 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in arm_smmu_init_domain_context()
794 cfg->vmid = cfg->cbndx + 1; in arm_smmu_init_domain_context()
796 cfg->asid = cfg->cbndx; in arm_smmu_init_domain_context()
799 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_init_domain_context()
802 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK, in arm_smmu_init_domain_context()
803 .tlb = smmu_domain->flush_ops, in arm_smmu_init_domain_context()
804 .iommu_dev = smmu->dev, in arm_smmu_init_domain_context()
807 if (smmu->impl && smmu->impl->init_context) { in arm_smmu_init_domain_context()
808 ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev); in arm_smmu_init_domain_context()
813 if (smmu_domain->pgtbl_quirks) in arm_smmu_init_domain_context()
814 pgtbl_cfg.quirks |= smmu_domain->pgtbl_quirks; in arm_smmu_init_domain_context()
818 ret = -ENOMEM; in arm_smmu_init_domain_context()
823 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; in arm_smmu_init_domain_context()
826 domain->geometry.aperture_start = ~0UL << ias; in arm_smmu_init_domain_context()
827 domain->geometry.aperture_end = ~0UL; in arm_smmu_init_domain_context()
829 domain->geometry.aperture_end = (1UL << ias) - 1; in arm_smmu_init_domain_context()
832 domain->geometry.force_aperture = true; in arm_smmu_init_domain_context()
836 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_init_domain_context()
840 * handler seeing a half-initialised domain state. in arm_smmu_init_domain_context()
842 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_init_domain_context()
844 if (smmu->impl && smmu->impl->context_fault) in arm_smmu_init_domain_context()
845 context_fault = smmu->impl->context_fault; in arm_smmu_init_domain_context()
849 if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) in arm_smmu_init_domain_context()
850 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_init_domain_context()
853 "arm-smmu-context-fault", in arm_smmu_init_domain_context()
856 ret = devm_request_irq(smmu->dev, irq, context_fault, IRQF_SHARED, in arm_smmu_init_domain_context()
857 "arm-smmu-context-fault", smmu_domain); in arm_smmu_init_domain_context()
860 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", in arm_smmu_init_domain_context()
861 cfg->irptndx, irq); in arm_smmu_init_domain_context()
862 cfg->irptndx = ARM_SMMU_INVALID_IRPTNDX; in arm_smmu_init_domain_context()
865 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_init_domain_context()
868 smmu_domain->pgtbl_ops = pgtbl_ops; in arm_smmu_init_domain_context()
872 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_init_domain_context()
873 smmu_domain->smmu = NULL; in arm_smmu_init_domain_context()
875 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_init_domain_context()
881 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_destroy_domain_context() local
882 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_destroy_domain_context()
885 if (!smmu) in arm_smmu_destroy_domain_context()
888 ret = arm_smmu_rpm_get(smmu); in arm_smmu_destroy_domain_context()
896 smmu->cbs[cfg->cbndx].cfg = NULL; in arm_smmu_destroy_domain_context()
897 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_destroy_domain_context()
899 if (cfg->irptndx != ARM_SMMU_INVALID_IRPTNDX) { in arm_smmu_destroy_domain_context()
900 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_destroy_domain_context()
901 devm_free_irq(smmu->dev, irq, smmu_domain); in arm_smmu_destroy_domain_context()
904 free_io_pgtable_ops(smmu_domain->pgtbl_ops); in arm_smmu_destroy_domain_context()
905 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_destroy_domain_context()
907 arm_smmu_rpm_put(smmu); in arm_smmu_destroy_domain_context()
923 mutex_init(&smmu_domain->init_mutex); in arm_smmu_domain_alloc_paging()
924 spin_lock_init(&smmu_domain->cb_lock); in arm_smmu_domain_alloc_paging()
926 return &smmu_domain->domain; in arm_smmu_domain_alloc_paging()
941 static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_smr() argument
943 struct arm_smmu_smr *smr = smmu->smrs + idx; in arm_smmu_write_smr()
944 u32 reg = FIELD_PREP(ARM_SMMU_SMR_ID, smr->id) | in arm_smmu_write_smr()
945 FIELD_PREP(ARM_SMMU_SMR_MASK, smr->mask); in arm_smmu_write_smr()
947 if (!(smmu->features & ARM_SMMU_FEAT_EXIDS) && smr->valid) in arm_smmu_write_smr()
949 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), reg); in arm_smmu_write_smr()
952 static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_s2cr() argument
954 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in arm_smmu_write_s2cr()
957 if (smmu->impl && smmu->impl->write_s2cr) { in arm_smmu_write_s2cr()
958 smmu->impl->write_s2cr(smmu, idx); in arm_smmu_write_s2cr()
962 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, s2cr->type) | in arm_smmu_write_s2cr()
963 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, s2cr->cbndx) | in arm_smmu_write_s2cr()
964 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); in arm_smmu_write_s2cr()
966 if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs && in arm_smmu_write_s2cr()
967 smmu->smrs[idx].valid) in arm_smmu_write_s2cr()
969 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in arm_smmu_write_s2cr()
972 static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_sme() argument
974 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_write_sme()
975 if (smmu->smrs) in arm_smmu_write_sme()
976 arm_smmu_write_smr(smmu, idx); in arm_smmu_write_sme()
983 static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) in arm_smmu_test_smr_masks() argument
988 if (!smmu->smrs) in arm_smmu_test_smr_masks()
998 for (i = 0; i < smmu->num_mapping_groups; i++) in arm_smmu_test_smr_masks()
999 if (!smmu->smrs[i].valid) in arm_smmu_test_smr_masks()
1008 smr = FIELD_PREP(ARM_SMMU_SMR_ID, smmu->streamid_mask); in arm_smmu_test_smr_masks()
1009 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
1010 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
1011 smmu->streamid_mask = FIELD_GET(ARM_SMMU_SMR_ID, smr); in arm_smmu_test_smr_masks()
1013 smr = FIELD_PREP(ARM_SMMU_SMR_MASK, smmu->streamid_mask); in arm_smmu_test_smr_masks()
1014 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
1015 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
1016 smmu->smr_mask_mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in arm_smmu_test_smr_masks()
1019 static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) in arm_smmu_find_sme() argument
1021 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_find_sme()
1022 int i, free_idx = -ENOSPC; in arm_smmu_find_sme()
1029 for (i = 0; i < smmu->num_mapping_groups; ++i) { in arm_smmu_find_sme()
1055 return -EINVAL; in arm_smmu_find_sme()
1061 static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_free_sme() argument
1063 if (--smmu->s2crs[idx].count) in arm_smmu_free_sme()
1066 smmu->s2crs[idx] = s2cr_init_val; in arm_smmu_free_sme()
1067 if (smmu->smrs) in arm_smmu_free_sme()
1068 smmu->smrs[idx].valid = false; in arm_smmu_free_sme()
1077 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_alloc_smes() local
1078 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_master_alloc_smes()
1081 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1084 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); in arm_smmu_master_alloc_smes()
1085 u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, fwspec->ids[i]); in arm_smmu_master_alloc_smes()
1088 ret = -EEXIST; in arm_smmu_master_alloc_smes()
1092 ret = arm_smmu_find_sme(smmu, sid, mask); in arm_smmu_master_alloc_smes()
1097 if (smrs && smmu->s2crs[idx].count == 0) { in arm_smmu_master_alloc_smes()
1102 smmu->s2crs[idx].count++; in arm_smmu_master_alloc_smes()
1103 cfg->smendx[i] = (s16)idx; in arm_smmu_master_alloc_smes()
1108 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_alloc_smes()
1110 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1114 while (i--) { in arm_smmu_master_alloc_smes()
1115 arm_smmu_free_sme(smmu, cfg->smendx[i]); in arm_smmu_master_alloc_smes()
1116 cfg->smendx[i] = INVALID_SMENDX; in arm_smmu_master_alloc_smes()
1118 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1125 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_free_smes() local
1128 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1130 if (arm_smmu_free_sme(smmu, idx)) in arm_smmu_master_free_smes()
1131 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_free_smes()
1132 cfg->smendx[i] = INVALID_SMENDX; in arm_smmu_master_free_smes()
1134 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1141 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_install_s2crs() local
1142 struct arm_smmu_s2cr *s2cr = smmu->s2crs; in arm_smmu_master_install_s2crs()
1152 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_master_install_s2crs()
1161 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
1165 * FIXME: The arch/arm DMA API code tries to attach devices to its own in arm_smmu_attach_dev()
1166 * domains between of_xlate() and probe_device() - we have no way to cope in arm_smmu_attach_dev()
1167 * with that, so until ARM gets converted to rely on groups and default in arm_smmu_attach_dev()
1173 return -ENODEV; in arm_smmu_attach_dev()
1175 smmu = cfg->smmu; in arm_smmu_attach_dev()
1177 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev()
1182 ret = arm_smmu_init_domain_context(smmu_domain, smmu, dev); in arm_smmu_attach_dev()
1190 if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
1191 ret = -EINVAL; in arm_smmu_attach_dev()
1197 smmu_domain->cfg.cbndx, fwspec); in arm_smmu_attach_dev()
1198 arm_smmu_rpm_use_autosuspend(smmu); in arm_smmu_attach_dev()
1200 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev()
1209 struct arm_smmu_device *smmu; in arm_smmu_attach_dev_type() local
1213 return -ENODEV; in arm_smmu_attach_dev_type()
1214 smmu = cfg->smmu; in arm_smmu_attach_dev_type()
1216 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev_type()
1221 arm_smmu_rpm_use_autosuspend(smmu); in arm_smmu_attach_dev_type()
1222 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev_type()
1260 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_map_pages()
1261 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_map_pages() local
1265 return -ENODEV; in arm_smmu_map_pages()
1267 arm_smmu_rpm_get(smmu); in arm_smmu_map_pages()
1268 ret = ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, gfp, mapped); in arm_smmu_map_pages()
1269 arm_smmu_rpm_put(smmu); in arm_smmu_map_pages()
1278 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_unmap_pages()
1279 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_unmap_pages() local
1285 arm_smmu_rpm_get(smmu); in arm_smmu_unmap_pages()
1286 ret = ops->unmap_pages(ops, iova, pgsize, pgcount, iotlb_gather); in arm_smmu_unmap_pages()
1287 arm_smmu_rpm_put(smmu); in arm_smmu_unmap_pages()
1295 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_flush_iotlb_all() local
1297 if (smmu_domain->flush_ops) { in arm_smmu_flush_iotlb_all()
1298 arm_smmu_rpm_get(smmu); in arm_smmu_flush_iotlb_all()
1299 smmu_domain->flush_ops->tlb_flush_all(smmu_domain); in arm_smmu_flush_iotlb_all()
1300 arm_smmu_rpm_put(smmu); in arm_smmu_flush_iotlb_all()
1308 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iotlb_sync() local
1310 if (!smmu) in arm_smmu_iotlb_sync()
1313 arm_smmu_rpm_get(smmu); in arm_smmu_iotlb_sync()
1314 if (smmu->version == ARM_SMMU_V2 || in arm_smmu_iotlb_sync()
1315 smmu_domain->stage == ARM_SMMU_DOMAIN_S1) in arm_smmu_iotlb_sync()
1318 arm_smmu_tlb_sync_global(smmu); in arm_smmu_iotlb_sync()
1319 arm_smmu_rpm_put(smmu); in arm_smmu_iotlb_sync()
1326 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iova_to_phys_hard() local
1327 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_iova_to_phys_hard()
1328 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; in arm_smmu_iova_to_phys_hard()
1329 struct device *dev = smmu->dev; in arm_smmu_iova_to_phys_hard()
1334 int ret, idx = cfg->cbndx; in arm_smmu_iova_to_phys_hard()
1337 ret = arm_smmu_rpm_get(smmu); in arm_smmu_iova_to_phys_hard()
1341 spin_lock_irqsave(&smmu_domain->cb_lock, flags); in arm_smmu_iova_to_phys_hard()
1343 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_iova_to_phys_hard()
1344 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1346 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1348 reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR; in arm_smmu_iova_to_phys_hard()
1351 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); in arm_smmu_iova_to_phys_hard()
1355 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1356 return ops->iova_to_phys(ops, iova); in arm_smmu_iova_to_phys_hard()
1359 phys = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_PAR); in arm_smmu_iova_to_phys_hard()
1360 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); in arm_smmu_iova_to_phys_hard()
1369 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1378 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; in arm_smmu_iova_to_phys()
1383 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && in arm_smmu_iova_to_phys()
1384 smmu_domain->stage == ARM_SMMU_DOMAIN_S1) in arm_smmu_iova_to_phys()
1387 return ops->iova_to_phys(ops, iova); in arm_smmu_iova_to_phys()
1402 return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK || in arm_smmu_capable()
1423 struct arm_smmu_device *smmu = NULL; in arm_smmu_probe_device() local
1429 ret = arm_smmu_register_legacy_master(dev, &smmu); in arm_smmu_probe_device()
1432 * If dev->iommu_fwspec is initally NULL, arm_smmu_register_legacy_master() in arm_smmu_probe_device()
1440 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
1443 ret = -EINVAL; in arm_smmu_probe_device()
1444 for (i = 0; i < fwspec->num_ids; i++) { in arm_smmu_probe_device()
1445 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); in arm_smmu_probe_device()
1446 u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, fwspec->ids[i]); in arm_smmu_probe_device()
1448 if (sid & ~smmu->streamid_mask) { in arm_smmu_probe_device()
1449 dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1450 sid, smmu->streamid_mask); in arm_smmu_probe_device()
1453 if (mask & ~smmu->smr_mask_mask) { in arm_smmu_probe_device()
1454 dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1455 mask, smmu->smr_mask_mask); in arm_smmu_probe_device()
1460 ret = -ENOMEM; in arm_smmu_probe_device()
1466 cfg->smmu = smmu; in arm_smmu_probe_device()
1468 while (i--) in arm_smmu_probe_device()
1469 cfg->smendx[i] = INVALID_SMENDX; in arm_smmu_probe_device()
1471 ret = arm_smmu_rpm_get(smmu); in arm_smmu_probe_device()
1476 arm_smmu_rpm_put(smmu); in arm_smmu_probe_device()
1481 device_link_add(dev, smmu->dev, in arm_smmu_probe_device()
1484 return &smmu->iommu; in arm_smmu_probe_device()
1499 ret = arm_smmu_rpm_get(cfg->smmu); in arm_smmu_release_device()
1505 arm_smmu_rpm_put(cfg->smmu); in arm_smmu_release_device()
1513 struct arm_smmu_device *smmu; in arm_smmu_probe_finalize() local
1516 smmu = cfg->smmu; in arm_smmu_probe_finalize()
1518 if (smmu->impl && smmu->impl->probe_finalize) in arm_smmu_probe_finalize()
1519 smmu->impl->probe_finalize(smmu, dev); in arm_smmu_probe_finalize()
1526 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_device_group() local
1530 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1532 if (group && smmu->s2crs[idx].group && in arm_smmu_device_group()
1533 group != smmu->s2crs[idx].group) { in arm_smmu_device_group()
1534 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1535 return ERR_PTR(-EINVAL); in arm_smmu_device_group()
1538 group = smmu->s2crs[idx].group; in arm_smmu_device_group()
1542 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1556 smmu->s2crs[idx].group = group; in arm_smmu_device_group()
1558 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1568 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_set_pgtable_quirks()
1569 if (smmu_domain->smmu) in arm_smmu_set_pgtable_quirks()
1570 ret = -EPERM; in arm_smmu_set_pgtable_quirks()
1572 smmu_domain->pgtbl_quirks = quirks; in arm_smmu_set_pgtable_quirks()
1573 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_set_pgtable_quirks()
1583 if (args->args_count > 0) in arm_smmu_of_xlate()
1584 fwid |= FIELD_PREP(ARM_SMMU_SMR_ID, args->args[0]); in arm_smmu_of_xlate()
1586 if (args->args_count > 1) in arm_smmu_of_xlate()
1587 fwid |= FIELD_PREP(ARM_SMMU_SMR_MASK, args->args[1]); in arm_smmu_of_xlate()
1588 else if (!of_property_read_u32(args->np, "stream-match-mask", &mask)) in arm_smmu_of_xlate()
1605 list_add_tail(®ion->list, head); in arm_smmu_get_resv_regions()
1613 const struct arm_smmu_impl *impl = cfg->smmu->impl; in arm_smmu_def_domain_type()
1618 if (impl && impl->def_domain_type) in arm_smmu_def_domain_type()
1619 return impl->def_domain_type(dev); in arm_smmu_def_domain_type()
1636 .pgsize_bitmap = -1UL, /* Restricted during device attach */
1650 static void arm_smmu_device_reset(struct arm_smmu_device *smmu) in arm_smmu_device_reset() argument
1656 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_device_reset()
1657 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); in arm_smmu_device_reset()
1663 for (i = 0; i < smmu->num_mapping_groups; ++i) in arm_smmu_device_reset()
1664 arm_smmu_write_sme(smmu, i); in arm_smmu_device_reset()
1667 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_smmu_device_reset()
1668 arm_smmu_write_context_bank(smmu, i); in arm_smmu_device_reset()
1669 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); in arm_smmu_device_reset()
1673 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1674 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLNSNH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1676 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_device_reset()
1698 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_device_reset()
1701 if (smmu->features & ARM_SMMU_FEAT_EXIDS) in arm_smmu_device_reset()
1704 if (smmu->impl && smmu->impl->reset) in arm_smmu_device_reset()
1705 smmu->impl->reset(smmu); in arm_smmu_device_reset()
1708 arm_smmu_tlb_sync_global(smmu); in arm_smmu_device_reset()
1709 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_device_reset()
1731 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) in arm_smmu_device_cfg_probe() argument
1735 bool cttw_reg, cttw_fw = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_cfg_probe()
1738 dev_notice(smmu->dev, "probing hardware configuration...\n"); in arm_smmu_device_cfg_probe()
1739 dev_notice(smmu->dev, "SMMUv%d with:\n", in arm_smmu_device_cfg_probe()
1740 smmu->version == ARM_SMMU_V2 ? 2 : 1); in arm_smmu_device_cfg_probe()
1743 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID0); in arm_smmu_device_cfg_probe()
1752 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_cfg_probe()
1753 dev_notice(smmu->dev, "\tstage 1 translation\n"); in arm_smmu_device_cfg_probe()
1757 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_cfg_probe()
1758 dev_notice(smmu->dev, "\tstage 2 translation\n"); in arm_smmu_device_cfg_probe()
1762 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; in arm_smmu_device_cfg_probe()
1763 dev_notice(smmu->dev, "\tnested translation\n"); in arm_smmu_device_cfg_probe()
1766 if (!(smmu->features & in arm_smmu_device_cfg_probe()
1768 dev_err(smmu->dev, "\tno translation support!\n"); in arm_smmu_device_cfg_probe()
1769 return -ENODEV; in arm_smmu_device_cfg_probe()
1773 ((smmu->version < ARM_SMMU_V2) || !(id & ARM_SMMU_ID0_ATOSNS))) { in arm_smmu_device_cfg_probe()
1774 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; in arm_smmu_device_cfg_probe()
1775 dev_notice(smmu->dev, "\taddress translation ops\n"); in arm_smmu_device_cfg_probe()
1786 dev_notice(smmu->dev, "\t%scoherent table walk\n", in arm_smmu_device_cfg_probe()
1787 cttw_fw ? "" : "non-"); in arm_smmu_device_cfg_probe()
1789 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1793 if (smmu->version == ARM_SMMU_V2 && id & ARM_SMMU_ID0_EXIDS) { in arm_smmu_device_cfg_probe()
1794 smmu->features |= ARM_SMMU_FEAT_EXIDS; in arm_smmu_device_cfg_probe()
1799 smmu->streamid_mask = size - 1; in arm_smmu_device_cfg_probe()
1801 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; in arm_smmu_device_cfg_probe()
1804 dev_err(smmu->dev, in arm_smmu_device_cfg_probe()
1805 "stream-matching supported, but no SMRs present!\n"); in arm_smmu_device_cfg_probe()
1806 return -ENODEV; in arm_smmu_device_cfg_probe()
1809 /* Zero-initialised to mark as invalid */ in arm_smmu_device_cfg_probe()
1810 smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs), in arm_smmu_device_cfg_probe()
1812 if (!smmu->smrs) in arm_smmu_device_cfg_probe()
1813 return -ENOMEM; in arm_smmu_device_cfg_probe()
1815 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1818 /* s2cr->type == 0 means translation, so initialise explicitly */ in arm_smmu_device_cfg_probe()
1819 smmu->s2crs = devm_kmalloc_array(smmu->dev, size, sizeof(*smmu->s2crs), in arm_smmu_device_cfg_probe()
1821 if (!smmu->s2crs) in arm_smmu_device_cfg_probe()
1822 return -ENOMEM; in arm_smmu_device_cfg_probe()
1824 smmu->s2crs[i] = s2cr_init_val; in arm_smmu_device_cfg_probe()
1826 smmu->num_mapping_groups = size; in arm_smmu_device_cfg_probe()
1827 mutex_init(&smmu->stream_map_mutex); in arm_smmu_device_cfg_probe()
1828 spin_lock_init(&smmu->global_sync_lock); in arm_smmu_device_cfg_probe()
1830 if (smmu->version < ARM_SMMU_V2 || in arm_smmu_device_cfg_probe()
1832 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L; in arm_smmu_device_cfg_probe()
1834 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S; in arm_smmu_device_cfg_probe()
1838 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID1); in arm_smmu_device_cfg_probe()
1839 smmu->pgshift = (id & ARM_SMMU_ID1_PAGESIZE) ? 16 : 12; in arm_smmu_device_cfg_probe()
1841 /* Check for size mismatch of SMMU address space from mapped region */ in arm_smmu_device_cfg_probe()
1843 if (smmu->numpage != 2 * size << smmu->pgshift) in arm_smmu_device_cfg_probe()
1844 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1845 "SMMU address space size (0x%x) differs from mapped region size (0x%x)!\n", in arm_smmu_device_cfg_probe()
1846 2 * size << smmu->pgshift, smmu->numpage); in arm_smmu_device_cfg_probe()
1848 smmu->numpage = size; in arm_smmu_device_cfg_probe()
1850 smmu->num_s2_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMS2CB, id); in arm_smmu_device_cfg_probe()
1851 smmu->num_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMCB, id); in arm_smmu_device_cfg_probe()
1852 if (smmu->num_s2_context_banks > smmu->num_context_banks) { in arm_smmu_device_cfg_probe()
1853 dev_err(smmu->dev, "impossible number of S2 context banks!\n"); in arm_smmu_device_cfg_probe()
1854 return -ENODEV; in arm_smmu_device_cfg_probe()
1856 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", in arm_smmu_device_cfg_probe()
1857 smmu->num_context_banks, smmu->num_s2_context_banks); in arm_smmu_device_cfg_probe()
1858 smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks, in arm_smmu_device_cfg_probe()
1859 sizeof(*smmu->cbs), GFP_KERNEL); in arm_smmu_device_cfg_probe()
1860 if (!smmu->cbs) in arm_smmu_device_cfg_probe()
1861 return -ENOMEM; in arm_smmu_device_cfg_probe()
1864 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID2); in arm_smmu_device_cfg_probe()
1866 smmu->ipa_size = size; in arm_smmu_device_cfg_probe()
1870 smmu->pa_size = size; in arm_smmu_device_cfg_probe()
1873 smmu->features |= ARM_SMMU_FEAT_VMID16; in arm_smmu_device_cfg_probe()
1880 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size))) in arm_smmu_device_cfg_probe()
1881 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1884 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_device_cfg_probe()
1885 smmu->va_size = smmu->ipa_size; in arm_smmu_device_cfg_probe()
1886 if (smmu->version == ARM_SMMU_V1_64K) in arm_smmu_device_cfg_probe()
1887 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1890 smmu->va_size = arm_smmu_id_size_to_bits(size); in arm_smmu_device_cfg_probe()
1892 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K; in arm_smmu_device_cfg_probe()
1894 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K; in arm_smmu_device_cfg_probe()
1896 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1899 if (smmu->impl && smmu->impl->cfg_probe) { in arm_smmu_device_cfg_probe()
1900 ret = smmu->impl->cfg_probe(smmu); in arm_smmu_device_cfg_probe()
1906 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) in arm_smmu_device_cfg_probe()
1907 smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; in arm_smmu_device_cfg_probe()
1908 if (smmu->features & in arm_smmu_device_cfg_probe()
1910 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_cfg_probe()
1911 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K) in arm_smmu_device_cfg_probe()
1912 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_cfg_probe()
1913 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K) in arm_smmu_device_cfg_probe()
1914 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_cfg_probe()
1916 if (arm_smmu_ops.pgsize_bitmap == -1UL) in arm_smmu_device_cfg_probe()
1917 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1919 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1920 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", in arm_smmu_device_cfg_probe()
1921 smmu->pgsize_bitmap); in arm_smmu_device_cfg_probe()
1924 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) in arm_smmu_device_cfg_probe()
1925 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", in arm_smmu_device_cfg_probe()
1926 smmu->va_size, smmu->ipa_size); in arm_smmu_device_cfg_probe()
1928 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) in arm_smmu_device_cfg_probe()
1929 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", in arm_smmu_device_cfg_probe()
1930 smmu->ipa_size, smmu->pa_size); in arm_smmu_device_cfg_probe()
1951 { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
1952 { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
1953 { .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
1954 { .compatible = "arm,mmu-401", .data = &arm_mmu401 },
1955 { .compatible = "arm,mmu-500", .data = &arm_mmu500 },
1956 { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
1957 { .compatible = "nvidia,smmu-500", .data = &arm_mmu500 },
1958 { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
1964 static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_data() argument
1971 smmu->version = ARM_SMMU_V1; in acpi_smmu_get_data()
1972 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1975 smmu->version = ARM_SMMU_V1_64K; in acpi_smmu_get_data()
1976 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1979 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1980 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1983 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1984 smmu->model = ARM_MMU500; in acpi_smmu_get_data()
1987 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1988 smmu->model = CAVIUM_SMMUV2; in acpi_smmu_get_data()
1991 ret = -ENODEV; in acpi_smmu_get_data()
1997 static int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
2000 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
2007 iort_smmu = (struct acpi_iort_smmu *)node->node_data; in arm_smmu_device_acpi_probe()
2009 ret = acpi_smmu_get_data(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
2017 if (iort_smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK) in arm_smmu_device_acpi_probe()
2018 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_acpi_probe()
2023 static inline int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
2026 return -ENODEV; in arm_smmu_device_acpi_probe()
2030 static int arm_smmu_device_dt_probe(struct arm_smmu_device *smmu, in arm_smmu_device_dt_probe() argument
2034 struct device *dev = smmu->dev; in arm_smmu_device_dt_probe()
2037 if (of_property_read_u32(dev->of_node, "#global-interrupts", global_irqs)) in arm_smmu_device_dt_probe()
2038 return dev_err_probe(dev, -ENODEV, in arm_smmu_device_dt_probe()
2039 "missing #global-interrupts property\n"); in arm_smmu_device_dt_probe()
2043 smmu->version = data->version; in arm_smmu_device_dt_probe()
2044 smmu->model = data->model; in arm_smmu_device_dt_probe()
2046 legacy_binding = of_find_property(dev->of_node, "mmu-masters", NULL); in arm_smmu_device_dt_probe()
2049 pr_notice("deprecated \"mmu-masters\" DT property in use; %s support unavailable\n", in arm_smmu_device_dt_probe()
2050 IS_ENABLED(CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS) ? "DMA API" : "SMMU"); in arm_smmu_device_dt_probe()
2057 return -ENODEV; in arm_smmu_device_dt_probe()
2060 if (of_dma_is_coherent(dev->of_node)) in arm_smmu_device_dt_probe()
2061 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_dt_probe()
2066 static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu) in arm_smmu_rmr_install_bypass_smr() argument
2074 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2080 * SMMU until it gets enabled again in the reset routine. in arm_smmu_rmr_install_bypass_smr()
2082 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_rmr_install_bypass_smr()
2084 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_rmr_install_bypass_smr()
2091 for (i = 0; i < rmr->num_sids; i++) { in arm_smmu_rmr_install_bypass_smr()
2092 idx = arm_smmu_find_sme(smmu, rmr->sids[i], ~0); in arm_smmu_rmr_install_bypass_smr()
2096 if (smmu->s2crs[idx].count == 0) { in arm_smmu_rmr_install_bypass_smr()
2097 smmu->smrs[idx].id = rmr->sids[i]; in arm_smmu_rmr_install_bypass_smr()
2098 smmu->smrs[idx].mask = 0; in arm_smmu_rmr_install_bypass_smr()
2099 smmu->smrs[idx].valid = true; in arm_smmu_rmr_install_bypass_smr()
2101 smmu->s2crs[idx].count++; in arm_smmu_rmr_install_bypass_smr()
2102 smmu->s2crs[idx].type = S2CR_TYPE_BYPASS; in arm_smmu_rmr_install_bypass_smr()
2103 smmu->s2crs[idx].privcfg = S2CR_PRIVCFG_DEFAULT; in arm_smmu_rmr_install_bypass_smr()
2109 dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt, in arm_smmu_rmr_install_bypass_smr()
2111 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2117 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
2118 struct device *dev = &pdev->dev; in arm_smmu_device_probe()
2123 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
2124 if (!smmu) { in arm_smmu_device_probe()
2126 return -ENOMEM; in arm_smmu_device_probe()
2128 smmu->dev = dev; in arm_smmu_device_probe()
2130 if (dev->of_node) in arm_smmu_device_probe()
2131 err = arm_smmu_device_dt_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2133 err = arm_smmu_device_acpi_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2137 smmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in arm_smmu_device_probe()
2138 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
2139 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
2140 smmu->ioaddr = res->start; in arm_smmu_device_probe()
2146 smmu->numpage = resource_size(res); in arm_smmu_device_probe()
2148 smmu = arm_smmu_impl_init(smmu); in arm_smmu_device_probe()
2149 if (IS_ERR(smmu)) in arm_smmu_device_probe()
2150 return PTR_ERR(smmu); in arm_smmu_device_probe()
2154 smmu->num_context_irqs = num_irqs - global_irqs - pmu_irqs; in arm_smmu_device_probe()
2155 if (smmu->num_context_irqs <= 0) in arm_smmu_device_probe()
2156 return dev_err_probe(dev, -ENODEV, in arm_smmu_device_probe()
2160 smmu->irqs = devm_kcalloc(dev, smmu->num_context_irqs, in arm_smmu_device_probe()
2161 sizeof(*smmu->irqs), GFP_KERNEL); in arm_smmu_device_probe()
2162 if (!smmu->irqs) in arm_smmu_device_probe()
2163 return dev_err_probe(dev, -ENOMEM, "failed to allocate %d irqs\n", in arm_smmu_device_probe()
2164 smmu->num_context_irqs); in arm_smmu_device_probe()
2166 for (i = 0; i < smmu->num_context_irqs; i++) { in arm_smmu_device_probe()
2171 smmu->irqs[i] = irq; in arm_smmu_device_probe()
2174 err = devm_clk_bulk_get_all(dev, &smmu->clks); in arm_smmu_device_probe()
2179 smmu->num_clks = err; in arm_smmu_device_probe()
2181 err = clk_bulk_prepare_enable(smmu->num_clks, smmu->clks); in arm_smmu_device_probe()
2185 err = arm_smmu_device_cfg_probe(smmu); in arm_smmu_device_probe()
2189 if (smmu->version == ARM_SMMU_V2) { in arm_smmu_device_probe()
2190 if (smmu->num_context_banks > smmu->num_context_irqs) { in arm_smmu_device_probe()
2193 smmu->num_context_irqs, smmu->num_context_banks); in arm_smmu_device_probe()
2194 return -ENODEV; in arm_smmu_device_probe()
2198 smmu->num_context_irqs = smmu->num_context_banks; in arm_smmu_device_probe()
2201 if (smmu->impl && smmu->impl->global_fault) in arm_smmu_device_probe()
2202 global_fault = smmu->impl->global_fault; in arm_smmu_device_probe()
2213 "arm-smmu global fault", smmu); in arm_smmu_device_probe()
2220 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
2223 arm_smmu_rmr_install_bypass_smr(smmu); in arm_smmu_device_probe()
2225 arm_smmu_device_reset(smmu); in arm_smmu_device_probe()
2226 arm_smmu_test_smr_masks(smmu); in arm_smmu_device_probe()
2228 err = iommu_device_sysfs_add(&smmu->iommu, smmu->dev, NULL, in arm_smmu_device_probe()
2229 "smmu.%pa", &smmu->ioaddr); in arm_smmu_device_probe()
2233 err = iommu_device_register(&smmu->iommu, &arm_smmu_ops, in arm_smmu_device_probe()
2236 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
2241 * We want to avoid touching dev->power.lock in fastpaths unless in arm_smmu_device_probe()
2242 * it's really going to do something useful - pm_runtime_enabled() in arm_smmu_device_probe()
2246 if (dev->pm_domain) { in arm_smmu_device_probe()
2256 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_shutdown() local
2258 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) in arm_smmu_device_shutdown()
2259 dev_notice(&pdev->dev, "disabling translation\n"); in arm_smmu_device_shutdown()
2261 arm_smmu_rpm_get(smmu); in arm_smmu_device_shutdown()
2263 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, ARM_SMMU_sCR0_CLIENTPD); in arm_smmu_device_shutdown()
2264 arm_smmu_rpm_put(smmu); in arm_smmu_device_shutdown()
2266 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_device_shutdown()
2267 pm_runtime_force_suspend(smmu->dev); in arm_smmu_device_shutdown()
2269 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2271 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2276 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
2278 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
2279 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
2286 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_resume() local
2289 ret = clk_bulk_enable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_resume()
2293 arm_smmu_device_reset(smmu); in arm_smmu_runtime_resume()
2300 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_suspend() local
2302 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_suspend()
2310 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_resume() local
2312 ret = clk_bulk_prepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2321 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2329 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_suspend() local
2339 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_suspend()
2351 .name = "arm-smmu",
2362 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2364 MODULE_ALIAS("platform:arm-smmu");