1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
17 #define QCOM_DUMMY_VAL	-1
20  * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
38 	{ .compatible = "qcom,adreno-gmu",
40 	{ .compatible = "qcom,adreno-smmu",
44 	{ .compatible = "qcom,sc7280-mdss",
46 	{ .compatible = "qcom,sc7280-venus",
48 	{ .compatible = "qcom,sm8550-mdss",
66 		for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {  in qcom_smmu_tlb_sync()
89 	if (qsmmu->stall_enabled & BIT(idx))  in qcom_adreno_smmu_write_sctlr()
99 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_get_fault_info()
100 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_get_fault_info()
102 	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);  in qcom_adreno_smmu_get_fault_info()
103 	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);  in qcom_adreno_smmu_get_fault_info()
104 	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);  in qcom_adreno_smmu_get_fault_info()
105 	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);  in qcom_adreno_smmu_get_fault_info()
106 	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));  in qcom_adreno_smmu_get_fault_info()
107 	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);  in qcom_adreno_smmu_get_fault_info()
108 	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);  in qcom_adreno_smmu_get_fault_info()
114 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_set_stall()
115 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);  in qcom_adreno_smmu_set_stall()
118 		qsmmu->stall_enabled |= BIT(cfg->cbndx);  in qcom_adreno_smmu_set_stall()
120 		qsmmu->stall_enabled &= ~BIT(cfg->cbndx);  in qcom_adreno_smmu_set_stall()
126 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_resume_translation()
127 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_resume_translation()
133 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);  in qcom_adreno_smmu_resume_translation()
139 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_set_prr_bit()
140 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_set_prr_bit()
144 	ret = pm_runtime_resume_and_get(smmu->dev);  in qcom_adreno_smmu_set_prr_bit()
146 		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);  in qcom_adreno_smmu_set_prr_bit()
150 	reg =  arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);  in qcom_adreno_smmu_set_prr_bit()
154 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);  in qcom_adreno_smmu_set_prr_bit()
155 	pm_runtime_put_autosuspend(smmu->dev);  in qcom_adreno_smmu_set_prr_bit()
161 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_set_prr_addr()
164 	ret = pm_runtime_resume_and_get(smmu->dev);  in qcom_adreno_smmu_set_prr_addr()
166 		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);  in qcom_adreno_smmu_set_prr_addr()
171 				smmu->base + ARM_SMMU_GFX_PRR_CFG_LADDR);  in qcom_adreno_smmu_set_prr_addr()
173 				smmu->base + ARM_SMMU_GFX_PRR_CFG_UADDR);  in qcom_adreno_smmu_set_prr_addr()
174 	pm_runtime_put_autosuspend(smmu->dev);  in qcom_adreno_smmu_set_prr_addr()
186 	 * identify it and configure it for per-instance pagetables  in qcom_adreno_smmu_is_gpu_device()
188 	for (i = 0; i < fwspec->num_ids; i++) {  in qcom_adreno_smmu_is_gpu_device()
189 		u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);  in qcom_adreno_smmu_is_gpu_device()
203 		io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);  in qcom_adreno_smmu_get_ttbr1_cfg()
204 	return &pgtable->cfg;  in qcom_adreno_smmu_get_ttbr1_cfg()
209  * The GPU driver will call this to enable TTBR0 when per-instance pagetables
217 	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);  in qcom_adreno_smmu_set_ttbr0_cfg()
218 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_set_ttbr0_cfg()
219 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in qcom_adreno_smmu_set_ttbr0_cfg()
222 	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)  in qcom_adreno_smmu_set_ttbr0_cfg()
223 		return -EINVAL;  in qcom_adreno_smmu_set_ttbr0_cfg()
228 		if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))  in qcom_adreno_smmu_set_ttbr0_cfg()
229 			return -EINVAL;  in qcom_adreno_smmu_set_ttbr0_cfg()
232 		cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);  in qcom_adreno_smmu_set_ttbr0_cfg()
233 		cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);  in qcom_adreno_smmu_set_ttbr0_cfg()
235 		u32 tcr = cb->tcr[0];  in qcom_adreno_smmu_set_ttbr0_cfg()
238 		if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))  in qcom_adreno_smmu_set_ttbr0_cfg()
239 			return -EINVAL;  in qcom_adreno_smmu_set_ttbr0_cfg()
244 		cb->tcr[0] = tcr;  in qcom_adreno_smmu_set_ttbr0_cfg()
245 		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;  in qcom_adreno_smmu_set_ttbr0_cfg()
246 		cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);  in qcom_adreno_smmu_set_ttbr0_cfg()
249 	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);  in qcom_adreno_smmu_set_ttbr0_cfg()
269 		count = smmu->num_context_banks;  in qcom_adreno_smmu_alloc_context_bank()
272 	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);  in qcom_adreno_smmu_alloc_context_bank()
277 	const struct device_node *np = smmu->dev->of_node;  in qcom_adreno_can_do_ttbr1()
279 	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))  in qcom_adreno_can_do_ttbr1()
296 	arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, (unsigned long)match->data);  in qcom_smmu_set_actlr_dev()
302 	const struct device_node *np = smmu_domain->smmu->dev->of_node;  in qcom_adreno_smmu_init_context()
303 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_init_context()
306 	int cbndx = smmu_domain->cfg.cbndx;  in qcom_adreno_smmu_init_context()
309 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;  in qcom_adreno_smmu_init_context()
311 	client_match = qsmmu->data->client_match;  in qcom_adreno_smmu_init_context()
321 	 * All targets that use the qcom,adreno-smmu compatible string *should*  in qcom_adreno_smmu_init_context()
322 	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes  in qcom_adreno_smmu_init_context()
325 	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&  in qcom_adreno_smmu_init_context()
326 	    (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&  in qcom_adreno_smmu_init_context()
327 	    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))  in qcom_adreno_smmu_init_context()
328 		pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;  in qcom_adreno_smmu_init_context()
335 	priv->cookie = smmu_domain;  in qcom_adreno_smmu_init_context()
336 	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;  in qcom_adreno_smmu_init_context()
337 	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;  in qcom_adreno_smmu_init_context()
338 	priv->get_fault_info = qcom_adreno_smmu_get_fault_info;  in qcom_adreno_smmu_init_context()
339 	priv->set_stall = qcom_adreno_smmu_set_stall;  in qcom_adreno_smmu_init_context()
340 	priv->resume_translation = qcom_adreno_smmu_resume_translation;  in qcom_adreno_smmu_init_context()
341 	priv->set_prr_bit = NULL;  in qcom_adreno_smmu_init_context()
342 	priv->set_prr_addr = NULL;  in qcom_adreno_smmu_init_context()
344 	if (of_device_is_compatible(np, "qcom,smmu-500") &&  in qcom_adreno_smmu_init_context()
345 			of_device_is_compatible(np, "qcom,adreno-smmu")) {  in qcom_adreno_smmu_init_context()
346 		priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit;  in qcom_adreno_smmu_init_context()
347 		priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr;  in qcom_adreno_smmu_init_context()
355 	{ .compatible = "qcom,adreno-gmu" },
358 	{ .compatible = "qcom,qcm2290-mdss" },
359 	{ .compatible = "qcom,sc7180-mdss" },
360 	{ .compatible = "qcom,sc7180-mss-pil" },
361 	{ .compatible = "qcom,sc7280-mdss" },
362 	{ .compatible = "qcom,sc7280-mss-pil" },
363 	{ .compatible = "qcom,sc8180x-mdss" },
364 	{ .compatible = "qcom,sc8280xp-mdss" },
365 	{ .compatible = "qcom,sdm670-mdss" },
366 	{ .compatible = "qcom,sdm845-mdss" },
367 	{ .compatible = "qcom,sdm845-mss-pil" },
368 	{ .compatible = "qcom,sm6350-mdss" },
369 	{ .compatible = "qcom,sm6375-mdss" },
370 	{ .compatible = "qcom,sm8150-mdss" },
371 	{ .compatible = "qcom,sm8250-mdss" },
372 	{ .compatible = "qcom,x1e80100-mdss" },
379 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_smmu_init_context()
382 	int cbndx = smmu_domain->cfg.cbndx;  in qcom_smmu_init_context()
384 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;  in qcom_smmu_init_context()
386 	client_match = qsmmu->data->client_match;  in qcom_smmu_init_context()
406 	if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") &&  in qcom_smmu_cfg_probe()
407 	    smmu->num_context_banks == 13) {  in qcom_smmu_cfg_probe()
408 		smmu->num_context_banks = 12;  in qcom_smmu_cfg_probe()
409 	} else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) {  in qcom_smmu_cfg_probe()
410 		if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */  in qcom_smmu_cfg_probe()
411 			smmu->num_context_banks = 7;  in qcom_smmu_cfg_probe()
412 		else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */  in qcom_smmu_cfg_probe()
413 			smmu->num_context_banks = 13;  in qcom_smmu_cfg_probe()
423 	if (smmu->num_mapping_groups > 128) {  in qcom_smmu_cfg_probe()
424 		dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");  in qcom_smmu_cfg_probe()
425 		smmu->num_mapping_groups = 128;  in qcom_smmu_cfg_probe()
428 	last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);  in qcom_smmu_cfg_probe()
442 		qsmmu->bypass_quirk = true;  in qcom_smmu_cfg_probe()
443 		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;  in qcom_smmu_cfg_probe()
445 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);  in qcom_smmu_cfg_probe()
447 		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);  in qcom_smmu_cfg_probe()
450 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);  in qcom_smmu_cfg_probe()
453 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_smmu_cfg_probe()
459 			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_smmu_cfg_probe()
460 			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_smmu_cfg_probe()
461 			smmu->smrs[i].valid = true;  in qcom_smmu_cfg_probe()
463 			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;  in qcom_smmu_cfg_probe()
464 			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;  in qcom_smmu_cfg_probe()
465 			smmu->s2crs[i].cbndx = 0xff;  in qcom_smmu_cfg_probe()
475 	smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K;  in qcom_adreno_smmuv2_cfg_probe()
478 	if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") &&  in qcom_adreno_smmuv2_cfg_probe()
479 	    smmu->num_context_banks == 5)  in qcom_adreno_smmuv2_cfg_probe()
480 		smmu->num_context_banks = 2;  in qcom_adreno_smmuv2_cfg_probe()
487 	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;  in qcom_smmu_write_s2cr()
489 	u32 cbndx = s2cr->cbndx;  in qcom_smmu_write_s2cr()
490 	u32 type = s2cr->type;  in qcom_smmu_write_s2cr()
493 	if (qsmmu->bypass_quirk) {  in qcom_smmu_write_s2cr()
502 			cbndx = qsmmu->bypass_cbndx;  in qcom_smmu_write_s2cr()
516 	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);  in qcom_smmu_write_s2cr()
535 	 * To address performance degradation in non-real time clients,  in qcom_sdm845_smmu500_reset()
536 	 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,  in qcom_sdm845_smmu500_reset()
538 	 * call handlers to turn on/off the wait-for-safe logic.  in qcom_sdm845_smmu500_reset()
542 		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");  in qcom_sdm845_smmu500_reset()
602 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_create()
607 		return ERR_PTR(-EINVAL);  in qcom_smmu_create()
609 	if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))  in qcom_smmu_create()
610 		impl = data->adreno_impl;  in qcom_smmu_create()
612 		impl = data->impl;  in qcom_smmu_create()
619 		return ERR_PTR(dev_err_probe(smmu->dev, -EPROBE_DEFER,  in qcom_smmu_create()
622 	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);  in qcom_smmu_create()
624 		return ERR_PTR(-ENOMEM);  in qcom_smmu_create()
626 	qsmmu->smmu.impl = impl;  in qcom_smmu_create()
627 	qsmmu->data = data;  in qcom_smmu_create()
629 	return &qsmmu->smmu;  in qcom_smmu_create()
661 	 * by the separate sdm845-smmu-v2 device.
674  * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
675  * special handling and can not be covered by the qcom,smmu-500 entry.
678 	{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
679 	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
680 	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
681 	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
682 	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
683 	{ .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
684 	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
685 	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
686 	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
687 	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
688 	{ .compatible = "qcom,sdm670-smmu-v2", .data = &qcom_smmu_v2_data },
689 	{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
690 	{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
691 	{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
692 	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
693 	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
694 	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
695 	{ .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
696 	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
697 	{ .compatible = "qcom,sm7150-smmu-v2", .data = &qcom_smmu_v2_data },
698 	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
699 	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
700 	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
701 	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
702 	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
708 	{ "LENOVO", "CB-01   ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
716 	struct device *dev = &pdev->dev;  in qcom_smmu_tbu_probe()
725 	if (dev->pm_domain) {  in qcom_smmu_tbu_probe()
734 	{ .compatible = "qcom,sc7280-tbu" },
735 	{ .compatible = "qcom,sdm845-tbu" },
749 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_impl_init()
766 		return qcom_smmu_create(smmu, match->data);  in qcom_smmu_impl_init()
770 	 * qcom_smmu_impl_of_match[] table, and GPU per-process page-  in qcom_smmu_impl_init()
773 	WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),  in qcom_smmu_impl_init()
775 	     dev_name(smmu->dev));  in qcom_smmu_impl_init()