7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
20  * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
40 	{ .compatible = "qcom,adreno-smmu",
53 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)  in to_qcom_smmu()  argument
55 	return container_of(smmu, struct qcom_smmu, smmu);  in to_qcom_smmu()
58 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,  in qcom_smmu_tlb_sync()  argument
64 	arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);  in qcom_smmu_tlb_sync()
67 			reg = arm_smmu_readl(smmu, page, status);  in qcom_smmu_tlb_sync()
75 	qcom_smmu_tlb_sync_debug(smmu);  in qcom_smmu_tlb_sync()
78 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,  in qcom_adreno_smmu_write_sctlr()  argument
81 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_adreno_smmu_write_sctlr()
92 	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);  in qcom_adreno_smmu_write_sctlr()
100 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_get_fault_info()  local
102 	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);  in qcom_adreno_smmu_get_fault_info()
103 	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);  in qcom_adreno_smmu_get_fault_info()
104 	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);  in qcom_adreno_smmu_get_fault_info()
105 	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);  in qcom_adreno_smmu_get_fault_info()
106 	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));  in qcom_adreno_smmu_get_fault_info()
107 	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);  in qcom_adreno_smmu_get_fault_info()
108 	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);  in qcom_adreno_smmu_get_fault_info()
115 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);  in qcom_adreno_smmu_set_stall()
127 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_resume_translation()  local
133 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);  in qcom_adreno_smmu_resume_translation()
139 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_set_prr_bit()  local
144 	ret = pm_runtime_resume_and_get(smmu->dev);  in qcom_adreno_smmu_set_prr_bit()
146 		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);  in qcom_adreno_smmu_set_prr_bit()
150 	reg =  arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);  in qcom_adreno_smmu_set_prr_bit()
154 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);  in qcom_adreno_smmu_set_prr_bit()
155 	pm_runtime_put_autosuspend(smmu->dev);  in qcom_adreno_smmu_set_prr_bit()
161 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_set_prr_addr()  local
164 	ret = pm_runtime_resume_and_get(smmu->dev);  in qcom_adreno_smmu_set_prr_addr()
166 		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);  in qcom_adreno_smmu_set_prr_addr()
171 				smmu->base + ARM_SMMU_GFX_PRR_CFG_LADDR);  in qcom_adreno_smmu_set_prr_addr()
173 				smmu->base + ARM_SMMU_GFX_PRR_CFG_UADDR);  in qcom_adreno_smmu_set_prr_addr()
174 	pm_runtime_put_autosuspend(smmu->dev);  in qcom_adreno_smmu_set_prr_addr()
219 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in qcom_adreno_smmu_set_ttbr0_cfg()
249 	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);  in qcom_adreno_smmu_set_ttbr0_cfg()
255 					       struct arm_smmu_device *smmu,  in qcom_adreno_smmu_alloc_context_bank()  argument
269 		count = smmu->num_context_banks;  in qcom_adreno_smmu_alloc_context_bank()
272 	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);  in qcom_adreno_smmu_alloc_context_bank()
275 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)  in qcom_adreno_can_do_ttbr1()  argument
277 	const struct device_node *np = smmu->dev->of_node;  in qcom_adreno_can_do_ttbr1()
279 	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))  in qcom_adreno_can_do_ttbr1()
285 static void qcom_smmu_set_actlr_dev(struct device *dev, struct arm_smmu_device *smmu, int cbndx,  in qcom_smmu_set_actlr_dev()  argument
296 	arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, (unsigned long)match->data);  in qcom_smmu_set_actlr_dev()
302 	const struct device_node *np = smmu_domain->smmu->dev->of_node;  in qcom_adreno_smmu_init_context()
303 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_init_context()  local
304 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_adreno_smmu_init_context()
314 		qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match);  in qcom_adreno_smmu_init_context()
321 	 * All targets that use the qcom,adreno-smmu compatible string *should*  in qcom_adreno_smmu_init_context()
322 	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes  in qcom_adreno_smmu_init_context()
325 	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&  in qcom_adreno_smmu_init_context()
344 	if (of_device_is_compatible(np, "qcom,smmu-500") &&  in qcom_adreno_smmu_init_context()
345 			of_device_is_compatible(np, "qcom,adreno-smmu")) {  in qcom_adreno_smmu_init_context()
379 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_smmu_init_context()  local
380 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_init_context()
389 		qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match);  in qcom_smmu_init_context()
394 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)  in qcom_smmu_cfg_probe()  argument
396 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_cfg_probe()
403 	 * MSM8998 LPASS SMMU reports 13 context banks, but accessing  in qcom_smmu_cfg_probe()
406 	if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") &&  in qcom_smmu_cfg_probe()
407 	    smmu->num_context_banks == 13) {  in qcom_smmu_cfg_probe()
408 		smmu->num_context_banks = 12;  in qcom_smmu_cfg_probe()
409 	} else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) {  in qcom_smmu_cfg_probe()
410 		if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */  in qcom_smmu_cfg_probe()
411 			smmu->num_context_banks = 7;  in qcom_smmu_cfg_probe()
412 		else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */  in qcom_smmu_cfg_probe()
413 			smmu->num_context_banks = 13;  in qcom_smmu_cfg_probe()
417 	 * Some platforms support more than the Arm SMMU architected maximum of  in qcom_smmu_cfg_probe()
423 	if (smmu->num_mapping_groups > 128) {  in qcom_smmu_cfg_probe()
424 		dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");  in qcom_smmu_cfg_probe()
425 		smmu->num_mapping_groups = 128;  in qcom_smmu_cfg_probe()
428 	last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);  in qcom_smmu_cfg_probe()
439 	arm_smmu_gr0_write(smmu, last_s2cr, reg);  in qcom_smmu_cfg_probe()
440 	reg = arm_smmu_gr0_read(smmu, last_s2cr);  in qcom_smmu_cfg_probe()
443 		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;  in qcom_smmu_cfg_probe()
445 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);  in qcom_smmu_cfg_probe()
447 		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);  in qcom_smmu_cfg_probe()
450 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);  in qcom_smmu_cfg_probe()
453 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_smmu_cfg_probe()
454 		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));  in qcom_smmu_cfg_probe()
459 			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_smmu_cfg_probe()
460 			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_smmu_cfg_probe()
461 			smmu->smrs[i].valid = true;  in qcom_smmu_cfg_probe()
463 			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;  in qcom_smmu_cfg_probe()
464 			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;  in qcom_smmu_cfg_probe()
465 			smmu->s2crs[i].cbndx = 0xff;  in qcom_smmu_cfg_probe()
472 static int qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device *smmu)  in qcom_adreno_smmuv2_cfg_probe()  argument
475 	smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K;  in qcom_adreno_smmuv2_cfg_probe()
478 	if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") &&  in qcom_adreno_smmuv2_cfg_probe()
479 	    smmu->num_context_banks == 5)  in qcom_adreno_smmuv2_cfg_probe()
480 		smmu->num_context_banks = 2;  in qcom_adreno_smmuv2_cfg_probe()
485 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)  in qcom_smmu_write_s2cr()  argument
487 	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;  in qcom_smmu_write_s2cr()
488 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_write_s2cr()
517 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);  in qcom_smmu_write_s2cr()
528 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_sdm845_smmu500_reset()  argument
532 	arm_mmu500_reset(smmu);  in qcom_sdm845_smmu500_reset()
542 		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");  in qcom_sdm845_smmu500_reset()
599 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,  in qcom_smmu_create()  argument
602 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_create()
609 	if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))  in qcom_smmu_create()
615 		return smmu;  in qcom_smmu_create()
619 		return ERR_PTR(dev_err_probe(smmu->dev, -EPROBE_DEFER,  in qcom_smmu_create()
622 	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);  in qcom_smmu_create()
626 	qsmmu->smmu.impl = impl;  in qcom_smmu_create()
629 	return &qsmmu->smmu;  in qcom_smmu_create()
644  * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
660 	 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
661 	 * by the separate sdm845-smmu-v2 device.
674  * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
675  * special handling and can not be covered by the qcom,smmu-500 entry.
678 	{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
679 	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
680 	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
681 	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
682 	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
683 	{ .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
684 	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
685 	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
686 	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
687 	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
688 	{ .compatible = "qcom,sdm670-smmu-v2", .data = &qcom_smmu_v2_data },
689 	{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
690 	{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
691 	{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
692 	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
693 	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
694 	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
695 	{ .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
696 	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
697 	{ .compatible = "qcom,sm7150-smmu-v2", .data = &qcom_smmu_v2_data },
698 	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
699 	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
700 	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
701 	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
702 	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
708 	{ "LENOVO", "CB-01   ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
709 	{ "QCOM  ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
747 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)  in qcom_smmu_impl_init()  argument
749 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_impl_init()
760 			return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);  in qcom_smmu_impl_init()
766 		return qcom_smmu_create(smmu, match->data);  in qcom_smmu_impl_init()
773 	WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),  in qcom_smmu_impl_init()
775 	     dev_name(smmu->dev));  in qcom_smmu_impl_init()
777 	return smmu;  in qcom_smmu_impl_init()