Lines Matching full:51
144 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
174 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
194 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
214 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
253 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
293 #define STRTAB_STE_2_S2AA64 (1UL << 51)
299 #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)
320 #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
370 #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
419 #define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
446 #define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2)
481 #define EVTQ_3_IPA GENMASK_ULL(51, 12)
482 #define EVTQ_3_FETCH_ADDR GENMASK_ULL(51, 3)
490 #define PRIQ_0_SSID GENMASK_ULL(51, 32)