Lines Matching +full:- +full:1 +full:ul
1 /* SPDX-License-Identifier: GPL-2.0-only */
23 #define IDR0_ST_LVL_2LVL 1
31 #define IDR0_CD2L (1 << 19)
32 #define IDR0_VMID16 (1 << 18)
33 #define IDR0_PRI (1 << 16)
34 #define IDR0_SEV (1 << 14)
35 #define IDR0_MSI (1 << 13)
36 #define IDR0_ASID16 (1 << 12)
37 #define IDR0_ATS (1 << 10)
38 #define IDR0_HYP (1 << 9)
40 #define IDR0_HTTU_ACCESS 1
42 #define IDR0_COHACC (1 << 4)
46 #define IDR0_S1P (1 << 1)
47 #define IDR0_S2P (1 << 0)
50 #define IDR1_TABLES_PRESET (1 << 30)
51 #define IDR1_QUEUES_PRESET (1 << 29)
52 #define IDR1_REL (1 << 28)
53 #define IDR1_ATTR_TYPES_OVR (1 << 27)
61 #define IDR3_FWB (1 << 8)
62 #define IDR3_RIL (1 << 10)
66 #define IDR5_GRAN64K (1 << 6)
67 #define IDR5_GRAN16K (1 << 5)
68 #define IDR5_GRAN4K (1 << 4)
71 #define IDR5_OAS_36_BIT 1
78 #define IDR5_VAX_52_BIT 1
89 #define CR0_ATSCHK (1 << 4)
90 #define CR0_CMDQEN (1 << 3)
91 #define CR0_EVTQEN (1 << 2)
92 #define CR0_PRIQEN (1 << 1)
93 #define CR0_SMMUEN (1 << 0)
103 #define CR1_QUEUE_IC GENMASK(1, 0)
104 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
106 #define CR1_CACHE_WB 1
110 #define CR2_PTM (1 << 2)
111 #define CR2_RECINVSID (1 << 1)
112 #define CR2_E2H (1 << 0)
115 #define GBPA_UPDATE (1 << 31)
116 #define GBPA_ABORT (1 << 20)
119 #define IRQ_CTRL_EVTQ_IRQEN (1 << 2)
120 #define IRQ_CTRL_PRIQ_IRQEN (1 << 1)
121 #define IRQ_CTRL_GERROR_IRQEN (1 << 0)
126 #define GERROR_SFM_ERR (1 << 8)
127 #define GERROR_MSI_GERROR_ABT_ERR (1 << 7)
128 #define GERROR_MSI_PRIQ_ABT_ERR (1 << 6)
129 #define GERROR_MSI_EVTQ_ABT_ERR (1 << 5)
130 #define GERROR_MSI_CMDQ_ABT_ERR (1 << 4)
131 #define GERROR_PRIQ_ABT_ERR (1 << 3)
132 #define GERROR_EVTQ_ABT_ERR (1 << 2)
133 #define GERROR_CMDQ_ERR (1 << 0)
143 #define STRTAB_BASE_RA (1UL << 62)
149 #define STRTAB_BASE_CFG_FMT_2LVL 1
185 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
186 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
187 #define Q_OVERFLOW_FLAG (1U << 31)
189 #define Q_ENT(q, p) ((q)->base + \
190 Q_IDX(&((q)->llq), p) * \
191 (q)->ent_dwords)
193 #define Q_BASE_RWA (1UL << 62)
207 * Linear: Enough to cover 1 << IDR1.SIDSIZE entries
222 #define STRTAB_NUM_L2_STES (1 << STRTAB_SPLIT)
230 #define STRTAB_MAX_L1_ENTRIES (1 << 17)
242 #define STRTAB_STE_0_V (1UL << 0)
243 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
256 #define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
261 #define STRTAB_STE_1_S1C_CACHE_NC 0UL
262 #define STRTAB_STE_1_S1C_CACHE_WBRA 1UL
263 #define STRTAB_STE_1_S1C_CACHE_WT 2UL
264 #define STRTAB_STE_1_S1C_CACHE_WB 3UL
269 #define STRTAB_STE_1_S2FWB (1UL << 25)
270 #define STRTAB_STE_1_S1STALLD (1UL << 27)
273 #define STRTAB_STE_1_EATS_ABT 0UL
274 #define STRTAB_STE_1_EATS_TRANS 1UL
275 #define STRTAB_STE_1_EATS_S1CHK 2UL
278 #define STRTAB_STE_1_STRW_NSEL1 0UL
279 #define STRTAB_STE_1_STRW_EL2 2UL
282 #define STRTAB_STE_1_SHCFG_INCOMING 1UL
293 #define STRTAB_STE_2_S2AA64 (1UL << 51)
294 #define STRTAB_STE_2_S2ENDI (1UL << 52)
295 #define STRTAB_STE_2_S2PTW (1UL << 54)
296 #define STRTAB_STE_2_S2S (1UL << 57)
297 #define STRTAB_STE_2_S2R (1UL << 58)
319 #define CTXDESC_L1_DESC_V (1UL << 0)
351 #define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14)
352 #define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30)
354 #define CTXDESC_CD_0_ENDI (1UL << 15)
355 #define CTXDESC_CD_0_V (1UL << 31)
358 #define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38)
360 #define CTXDESC_CD_0_TCR_HA (1UL << 43)
361 #define CTXDESC_CD_0_TCR_HD (1UL << 42)
363 #define CTXDESC_CD_0_AA64 (1UL << 41)
364 #define CTXDESC_CD_0_S (1UL << 44)
365 #define CTXDESC_CD_0_R (1UL << 45)
366 #define CTXDESC_CD_0_A (1UL << 46)
367 #define CTXDESC_CD_0_ASET (1UL << 47)
380 #define CMDQ_ENT_DWORDS ((1 << CMDQ_ENT_SZ_SHIFT) >> 3)
381 #define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
385 #define CMDQ_ERR_CERROR_ILL_IDX 1
399 #define CMDQ_0_SSV (1UL << 11)
407 #define CMDQ_CFGI_1_LEAF (1UL << 0)
415 #define CMDQ_TLBI_1_LEAF (1UL << 0)
423 #define CMDQ_ATC_0_GLOBAL (1UL << 9)
432 #define CMDQ_RESUME_0_RESP_TERM 0UL
433 #define CMDQ_RESUME_0_RESP_RETRY 1UL
434 #define CMDQ_RESUME_0_RESP_ABORT 2UL
441 #define CMDQ_SYNC_0_CS_IRQ 1
450 #define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3)
451 #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
468 #define EVTQ_0_SSV (1UL << 11)
472 #define EVTQ_1_STALL (1UL << 31)
473 #define EVTQ_1_PnU (1UL << 33)
474 #define EVTQ_1_InD (1UL << 34)
475 #define EVTQ_1_RnW (1UL << 35)
476 #define EVTQ_1_S2 (1UL << 39)
479 #define EVTQ_1_TT_READ (1UL << 44)
486 #define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3)
487 #define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
491 #define PRIQ_0_PERM_PRIV (1UL << 58)
492 #define PRIQ_0_PERM_EXEC (1UL << 59)
493 #define PRIQ_0_PERM_READ (1UL << 60)
494 #define PRIQ_0_PERM_WRITE (1UL << 61)
495 #define PRIQ_0_PRG_LAST (1UL << 62)
496 #define PRIQ_0_SSID_V (1UL << 63)
501 /* High-level queue structures */
502 #define ARM_SMMU_POLL_TIMEOUT_US 1000000 /* 1s! */
510 PRI_RESP_FAIL = 1,
519 /* Command-specific fields */
640 return cmdq->supports_cmd ? cmdq->supports_cmd(ent) : true; in arm_smmu_cmdq_supports_cmd()
659 /* High-level stream table and context descriptor structures */
687 return cfg->linear.table || cfg->l2.l1tab; in arm_smmu_cdtab_allocated()
693 return cd_table->used_ssids; in arm_smmu_ssids_in_use()
733 #define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0)
734 #define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1)
735 #define ARM_SMMU_FEAT_TT_LE (1 << 2)
736 #define ARM_SMMU_FEAT_TT_BE (1 << 3)
737 #define ARM_SMMU_FEAT_PRI (1 << 4)
738 #define ARM_SMMU_FEAT_ATS (1 << 5)
739 #define ARM_SMMU_FEAT_SEV (1 << 6)
740 #define ARM_SMMU_FEAT_MSI (1 << 7)
741 #define ARM_SMMU_FEAT_COHERENCY (1 << 8)
742 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 9)
743 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 10)
744 #define ARM_SMMU_FEAT_STALLS (1 << 11)
745 #define ARM_SMMU_FEAT_HYP (1 << 12)
746 #define ARM_SMMU_FEAT_STALL_FORCE (1 << 13)
747 #define ARM_SMMU_FEAT_VAX (1 << 14)
748 #define ARM_SMMU_FEAT_RANGE_INV (1 << 15)
749 #define ARM_SMMU_FEAT_BTM (1 << 16)
750 #define ARM_SMMU_FEAT_SVA (1 << 17)
751 #define ARM_SMMU_FEAT_E2H (1 << 18)
752 #define ARM_SMMU_FEAT_NESTING (1 << 19)
753 #define ARM_SMMU_FEAT_ATTR_TYPES_OVR (1 << 20)
754 #define ARM_SMMU_FEAT_HA (1 << 21)
755 #define ARM_SMMU_FEAT_HD (1 << 22)
756 #define ARM_SMMU_FEAT_S2FWB (1 << 23)
759 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
760 #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1)
761 #define ARM_SMMU_OPT_MSIPOLL (1 << 2)
762 #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3)
763 #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4)
777 #define ARM_SMMU_MAX_ASIDS (1 << 16)
780 #define ARM_SMMU_MAX_VMIDS (1 << 16)
803 u8 stall : 1,
804 ssv : 1,
805 privileged : 1,
806 instruction : 1,
807 s2 : 1,
808 read : 1,
809 ttrnw : 1,
810 class_tt : 1;
830 bool ats_enabled : 1;
831 bool ste_ats_enabled : 1;
861 bool enforce_cache_coherency : 1;
862 bool nest_parent : 1;
870 bool enable_ats : 1;
912 bool nested_ats_flush : 1;
963 return dev_iommu_fwspec_get(master->dev)->flags & in arm_smmu_master_canwbs()
1016 return -ENODEV; in arm_smmu_master_enable_sva()
1021 return -ENODEV; in arm_smmu_master_disable_sva()
1041 return ERR_PTR(-ENODEV); in tegra241_cmdqv_probe()