65 	pr_debug("STE value is now set to: ");  in arm_smmu_test_writer_record_syncs()
96 				       const __le64 *ste)  in arm_smmu_v3_test_debug_print_used_bits()  argument
100 	arm_smmu_get_ste_used(ste, used_bits);  in arm_smmu_v3_test_debug_print_used_bits()
101 	pr_debug("STE used bits: ");  in arm_smmu_v3_test_debug_print_used_bits()
135 	pr_debug("STE initial value: ");  in arm_smmu_v3_test_ste_expect_transition()
139 	pr_debug("STE target value: ");  in arm_smmu_v3_test_ste_expect_transition()
170 static void arm_smmu_test_make_cdtable_ste(struct arm_smmu_ste *ste,  in arm_smmu_test_make_cdtable_ste()  argument
187 	arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss);  in arm_smmu_test_make_cdtable_ste()
196 	 * the STE into an abort, the second to clean up the second qword.  in arm_smmu_v3_write_ste_test_bypass_to_abort()
206 	 * to set the second qword data required by the bypass STE, and the  in arm_smmu_v3_write_ste_test_abort_to_bypass()
215 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_cdtable_to_abort()  local
217 	arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,  in arm_smmu_v3_write_ste_test_cdtable_to_abort()
219 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &abort_ste,  in arm_smmu_v3_write_ste_test_cdtable_to_abort()
225 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_abort_to_cdtable()  local
227 	arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,  in arm_smmu_v3_write_ste_test_abort_to_cdtable()
229 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &abort_ste, &ste,  in arm_smmu_v3_write_ste_test_abort_to_cdtable()
235 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_cdtable_to_bypass()  local
237 	arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,  in arm_smmu_v3_write_ste_test_cdtable_to_bypass()
239 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &bypass_ste,  in arm_smmu_v3_write_ste_test_cdtable_to_bypass()
245 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_bypass_to_cdtable()  local
247 	arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,  in arm_smmu_v3_write_ste_test_bypass_to_cdtable()
249 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &bypass_ste, &ste,  in arm_smmu_v3_write_ste_test_bypass_to_cdtable()
255 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()  local
258 	arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()
264 	 * Flipping s1dss on a CD table STE only involves changes to the second  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()
265 	 * qword of an STE and can be done in a single write.  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()
268 		test, &ste, &s1dss_bypass, NUM_EXPECTED_SYNCS(1));  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()
270 		test, &s1dss_bypass, &ste, NUM_EXPECTED_SYNCS(1));  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()
295 static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste,  in arm_smmu_test_make_s2_ste()  argument
319 	arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, ats_enabled);  in arm_smmu_test_make_s2_ste()
324 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_s2_to_abort()  local
326 	arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);  in arm_smmu_v3_write_ste_test_s2_to_abort()
327 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &abort_ste,  in arm_smmu_v3_write_ste_test_s2_to_abort()
333 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_abort_to_s2()  local
335 	arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);  in arm_smmu_v3_write_ste_test_abort_to_s2()
336 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &abort_ste, &ste,  in arm_smmu_v3_write_ste_test_abort_to_s2()
342 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_s2_to_bypass()  local
344 	arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);  in arm_smmu_v3_write_ste_test_s2_to_bypass()
345 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &bypass_ste,  in arm_smmu_v3_write_ste_test_s2_to_bypass()
351 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_bypass_to_s2()  local
353 	arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS);  in arm_smmu_v3_write_ste_test_bypass_to_s2()
354 	arm_smmu_v3_test_ste_expect_hitless_transition(test, &bypass_ste, &ste,  in arm_smmu_v3_write_ste_test_bypass_to_s2()
384 	struct arm_smmu_ste ste;  in arm_smmu_v3_write_ste_test_non_hitless()  local
388 	 * Although no flow resembles this in practice, one way to force an STE  in arm_smmu_v3_write_ste_test_non_hitless()
392 	arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0,  in arm_smmu_v3_write_ste_test_non_hitless()
397 		test, &ste, &ste_2, NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_non_hitless()