Lines Matching full:iommu
20 #include <linux/amd-iommu.h>
26 #include <asm/iommu.h>
39 #include "../iommu-pages.h"
99 * structure describing one IOMMU in the ACPI table. Typically followed by one
119 * A device entry describing which devices a specific IOMMU translates and
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
229 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
231 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
234 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
236 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
239 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
243 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
245 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
267 struct amd_iommu *iommu; in get_global_efr() local
269 for_each_iommu(iommu) { in get_global_efr()
270 u64 tmp = iommu->features; in get_global_efr()
271 u64 tmp2 = iommu->features2; in get_global_efr()
273 if (list_is_first(&iommu->list, &amd_iommu_list)) { in get_global_efr()
284 …"Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", in get_global_efr()
286 iommu->index, iommu->pci_seg->id, in get_global_efr()
287 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), in get_global_efr()
288 PCI_FUNC(iommu->devid)); in get_global_efr()
302 static void __init early_iommu_features_init(struct amd_iommu *iommu, in early_iommu_features_init() argument
306 iommu->features = h->efr_reg; in early_iommu_features_init()
307 iommu->features2 = h->efr_reg2; in early_iommu_features_init()
315 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
319 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
320 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
324 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
326 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
327 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
331 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
335 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
336 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
340 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
342 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
343 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
348 * AMD IOMMU MMIO register space handling functions
350 * These functions are used to program the IOMMU device registers in
356 * This function set the exclusion range in the IOMMU. DMA accesses to the
359 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
361 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
362 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
365 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
377 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
379 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
396 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
400 /* Programs the physical address of the device table into the IOMMU hardware */
401 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
404 u32 dev_table_size = iommu->pci_seg->dev_table_size; in iommu_set_device_table()
405 void *dev_table = (void *)get_dev_table(iommu); in iommu_set_device_table()
407 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
411 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
415 /* Generic functions to enable/disable certain features of the IOMMU. */
416 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
420 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
422 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
425 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
429 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
431 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
434 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
438 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
441 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
445 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
447 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
450 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
452 if (!iommu->mmio_base) in iommu_disable()
456 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
459 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
460 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
462 /* Disable IOMMU GA_LOG */ in iommu_disable()
463 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
464 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
466 /* Disable IOMMU PPR logging */ in iommu_disable()
467 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); in iommu_disable()
468 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); in iommu_disable()
470 /* Disable IOMMU hardware itself */ in iommu_disable()
471 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
474 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable()
478 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
493 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
495 if (iommu->mmio_base) in iommu_unmap_mmio_space()
496 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
497 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
518 * The functions below belong to the first pass of AMD IOMMU ACPI table
542 * After reading the highest device id from the IOMMU PCI capability header
637 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
661 /* Allocate per PCI segment IOMMU rlookup table. */
725 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
726 * write commands to that buffer later and the IOMMU will execute them
729 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
731 iommu->cmd_buf = iommu_alloc_pages(GFP_KERNEL, in alloc_command_buffer()
734 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
741 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, in amd_iommu_restart_log() argument
747 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
751 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); in amd_iommu_restart_log()
753 iommu_feature_disable(iommu, cntrl_log); in amd_iommu_restart_log()
754 iommu_feature_disable(iommu, cntrl_intr); in amd_iommu_restart_log()
756 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
758 iommu_feature_enable(iommu, cntrl_intr); in amd_iommu_restart_log()
759 iommu_feature_enable(iommu, cntrl_log); in amd_iommu_restart_log()
763 * This function restarts event logging in case the IOMMU experienced
766 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) in amd_iommu_restart_event_logging() argument
768 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, in amd_iommu_restart_event_logging()
774 * This function restarts event logging in case the IOMMU experienced
777 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) in amd_iommu_restart_ga_log() argument
779 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, in amd_iommu_restart_ga_log()
785 * This function resets the command buffer if the IOMMU stopped fetching
788 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
790 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
792 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
793 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
794 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
795 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
797 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
804 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
808 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
810 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
813 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
816 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
822 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
824 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
827 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
829 iommu_free_pages(iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
832 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, in iommu_alloc_4k_pages() argument
848 /* allocates the memory where the IOMMU will log its events to */
849 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
851 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, in alloc_event_buffer()
854 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
857 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
861 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
863 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
865 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
869 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
870 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
872 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
878 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
880 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
883 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
885 iommu_free_pages(iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
888 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
891 iommu_free_pages(iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
892 iommu_free_pages(iommu->ga_log_tail, get_order(8)); in free_ga_log()
897 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
902 if (!iommu->ga_log) in iommu_ga_log_enable()
905 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_ga_log_enable()
906 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_ga_log_enable()
908 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_ga_log_enable()
910 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_ga_log_enable()
912 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_ga_log_enable()
913 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_ga_log_enable()
916 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
917 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
920 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
932 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
937 iommu->ga_log = iommu_alloc_pages(GFP_KERNEL, get_order(GA_LOG_SIZE)); in iommu_init_ga_log()
938 if (!iommu->ga_log) in iommu_init_ga_log()
941 iommu->ga_log_tail = iommu_alloc_pages(GFP_KERNEL, get_order(8)); in iommu_init_ga_log()
942 if (!iommu->ga_log_tail) in iommu_init_ga_log()
947 free_ga_log(iommu); in iommu_init_ga_log()
952 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
954 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); in alloc_cwwb_sem()
956 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
959 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
961 if (iommu->cmd_sem) in free_cwwb_sem()
962 iommu_free_page((void *)iommu->cmd_sem); in free_cwwb_sem()
965 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
974 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
978 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
983 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
995 static bool __copy_device_table(struct amd_iommu *iommu) in __copy_device_table() argument
998 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in __copy_device_table()
1005 /* Each IOMMU use separate device table with the same size */ in __copy_device_table()
1006 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in __copy_device_table()
1007 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in __copy_device_table()
1012 pr_err("The device table size of IOMMU:%d is not expected!\n", in __copy_device_table()
1013 iommu->index); in __copy_device_table()
1088 struct amd_iommu *iommu; in copy_device_table() local
1101 for_each_iommu(iommu) { in copy_device_table()
1102 if (pci_seg->id != iommu->pci_seg->id) in copy_device_table()
1104 if (!__copy_device_table(iommu)) in copy_device_table()
1155 set_dev_entry_from_acpi_range(struct amd_iommu *iommu, u16 first, u16 last, in set_dev_entry_from_acpi_range() argument
1165 if (search_ivhd_dte_flags(iommu->pci_seg->id, first, last)) in set_dev_entry_from_acpi_range()
1194 d->segid = iommu->pci_seg->id; in set_dev_entry_from_acpi_range()
1202 struct dev_table_entry *dev_table = get_dev_table(iommu); in set_dev_entry_from_acpi_range()
1206 amd_iommu_set_rlookup_table(iommu, i); in set_dev_entry_from_acpi_range()
1210 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1213 set_dev_entry_from_acpi_range(iommu, devid, devid, flags, ext_flags); in set_dev_entry_from_acpi()
1324 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1327 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1336 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in init_iommu_from_acpi()
1350 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1374 set_dev_entry_from_acpi_range(iommu, 0, pci_seg->last_bdf, e->flags, 0); in init_iommu_from_acpi()
1385 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1413 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1414 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1443 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1471 set_dev_entry_from_acpi_range(iommu, devid_start, devid, flags, ext_flags); in init_iommu_from_acpi()
1472 set_dev_entry_from_acpi(iommu, devid_to, flags, ext_flags); in init_iommu_from_acpi()
1507 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1574 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1656 static void __init free_sysfs(struct amd_iommu *iommu) in free_sysfs() argument
1658 if (iommu->iommu.dev) { in free_sysfs()
1659 iommu_device_unregister(&iommu->iommu); in free_sysfs()
1660 iommu_device_sysfs_remove(&iommu->iommu); in free_sysfs()
1664 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1666 free_sysfs(iommu); in free_iommu_one()
1667 free_cwwb_sem(iommu); in free_iommu_one()
1668 free_command_buffer(iommu); in free_iommu_one()
1669 free_event_buffer(iommu); in free_iommu_one()
1670 amd_iommu_free_ppr_log(iommu); in free_iommu_one()
1671 free_ga_log(iommu); in free_iommu_one()
1672 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1673 amd_iommu_iopf_uninit(iommu); in free_iommu_one()
1678 struct amd_iommu *iommu, *next; in free_iommu_all() local
1680 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1681 list_del(&iommu->list); in free_iommu_all()
1682 free_iommu_one(iommu); in free_iommu_all()
1683 kfree(iommu); in free_iommu_all()
1688 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1693 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1702 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1703 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1709 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1711 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1712 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1715 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1719 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1724 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1734 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1740 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1742 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1746 * This function glues the initialization function for one IOMMU
1748 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1750 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, in init_iommu_one() argument
1758 iommu->pci_seg = pci_seg; in init_iommu_one()
1760 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1761 atomic64_set(&iommu->cmd_sem_val, 0); in init_iommu_one()
1763 /* Add IOMMU to internal data structures */ in init_iommu_one()
1764 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1765 iommu->index = amd_iommus_present++; in init_iommu_one()
1767 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1773 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1775 iommu->devid = h->devid; in init_iommu_one()
1776 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1777 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1785 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1787 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1796 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1798 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1809 early_iommu_features_init(iommu, h); in init_iommu_one()
1816 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1817 iommu->mmio_phys_end); in init_iommu_one()
1818 if (!iommu->mmio_base) in init_iommu_one()
1821 return init_iommu_from_acpi(iommu, h); in init_iommu_one()
1824 static int __init init_iommu_one_late(struct amd_iommu *iommu) in init_iommu_one_late() argument
1828 if (alloc_cwwb_sem(iommu)) in init_iommu_one_late()
1831 if (alloc_command_buffer(iommu)) in init_iommu_one_late()
1834 if (alloc_event_buffer(iommu)) in init_iommu_one_late()
1837 iommu->int_enabled = false; in init_iommu_one_late()
1839 init_translation_status(iommu); in init_iommu_one_late()
1840 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one_late()
1841 iommu_disable(iommu); in init_iommu_one_late()
1842 clear_translation_pre_enabled(iommu); in init_iommu_one_late()
1843 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one_late()
1844 iommu->index); in init_iommu_one_late()
1847 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one_late()
1850 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one_late()
1856 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one_late()
1859 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; in init_iommu_one_late()
1891 * Iterates over all IOMMU entries in the ACPI table, allocates the
1892 * IOMMU structure and initializes it with init_iommu_one()
1898 struct amd_iommu *iommu; in init_iommu_all() local
1917 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1918 if (iommu == NULL) in init_iommu_all()
1921 ret = init_iommu_one(iommu, h, table); in init_iommu_all()
1933 /* Phase 3 : Enabling IOMMU features */ in init_iommu_all()
1934 for_each_iommu(iommu) { in init_iommu_all()
1935 ret = init_iommu_one_late(iommu); in init_iommu_all()
1943 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1946 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1953 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
1955 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1956 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1957 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1966 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
1967 return sysfs_emit(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1986 .name = "amd-iommu",
1997 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
2000 static void __init late_iommu_features_init(struct amd_iommu *iommu) in late_iommu_features_init() argument
2004 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
2008 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
2009 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); in late_iommu_features_init()
2030 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
2032 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
2035 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2036 PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
2037 iommu->devid & 0xff); in iommu_init_pci()
2038 if (!iommu->dev) in iommu_init_pci()
2041 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
2042 iommu->dev->match_driver = false; in iommu_init_pci()
2044 /* ACPI _PRT won't have an IRQ for IOMMU */ in iommu_init_pci()
2045 iommu->dev->irq_managed = 1; in iommu_init_pci()
2047 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
2048 &iommu->cap); in iommu_init_pci()
2050 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
2053 late_iommu_features_init(iommu); in iommu_init_pci()
2060 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; in iommu_init_pci()
2062 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); in iommu_init_pci()
2071 iommu_enable_gt(iommu); in iommu_init_pci()
2074 if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) in iommu_init_pci()
2077 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { in iommu_init_pci()
2083 init_iommu_perf_ctr(iommu); in iommu_init_pci()
2085 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
2088 iommu->root_pdev = in iommu_init_pci()
2089 pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2090 iommu->dev->bus->number, in iommu_init_pci()
2098 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
2099 &iommu->stored_addr_lo); in iommu_init_pci()
2100 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
2101 &iommu->stored_addr_hi); in iommu_init_pci()
2104 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
2108 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
2111 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
2114 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
2115 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
2117 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
2118 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
2123 * Allocate per IOMMU IOPF queue here so that in attach device path, in iommu_init_pci()
2127 ret = amd_iommu_iopf_init(iommu); in iommu_init_pci()
2132 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); in iommu_init_pci()
2134 return pci_enable_device(iommu->dev); in iommu_init_pci()
2175 struct amd_iommu *iommu; in amd_iommu_init_pci() local
2179 /* Init global identity domain before registering IOMMU */ in amd_iommu_init_pci()
2182 for_each_iommu(iommu) { in amd_iommu_init_pci()
2183 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
2185 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", in amd_iommu_init_pci()
2186 iommu->index, ret); in amd_iommu_init_pci()
2190 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
2206 for_each_iommu(iommu) in amd_iommu_init_pci()
2207 amd_iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
2224 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
2228 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
2232 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
2236 iommu); in iommu_setup_msi()
2239 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2308 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_unmask_irq() local
2318 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); in intcapxt_unmask_irq()
2323 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_mask_irq() local
2325 writeq(0, iommu->mmio_base + irqd->hwirq); in intcapxt_mask_irq()
2347 .name = "IOMMU-MSI",
2388 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, in __iommu_setup_intcapxt() argument
2394 int node = dev_to_node(&iommu->dev->dev); in __iommu_setup_intcapxt()
2402 info.data = iommu; in __iommu_setup_intcapxt()
2412 thread_fn, 0, devname, iommu); in __iommu_setup_intcapxt()
2422 static int iommu_setup_intcapxt(struct amd_iommu *iommu) in iommu_setup_intcapxt() argument
2426 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), in iommu_setup_intcapxt()
2427 "AMD-Vi%d-Evt", iommu->index); in iommu_setup_intcapxt()
2428 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, in iommu_setup_intcapxt()
2434 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), in iommu_setup_intcapxt()
2435 "AMD-Vi%d-PPR", iommu->index); in iommu_setup_intcapxt()
2436 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, in iommu_setup_intcapxt()
2443 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), in iommu_setup_intcapxt()
2444 "AMD-Vi%d-GA", iommu->index); in iommu_setup_intcapxt()
2445 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, in iommu_setup_intcapxt()
2453 static int iommu_init_irq(struct amd_iommu *iommu) in iommu_init_irq() argument
2457 if (iommu->int_enabled) in iommu_init_irq()
2461 ret = iommu_setup_intcapxt(iommu); in iommu_init_irq()
2462 else if (iommu->dev->msi_cap) in iommu_init_irq()
2463 ret = iommu_setup_msi(iommu); in iommu_init_irq()
2470 iommu->int_enabled = true; in iommu_init_irq()
2474 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_init_irq()
2476 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_irq()
2631 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2633 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2634 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2635 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2637 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2638 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2639 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2641 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2642 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2643 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2645 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2646 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2647 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2650 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2652 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2655 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2659 iommu_feature_enable(iommu, CONTROL_EPH_EN); in iommu_init_flags()
2662 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2666 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2668 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2669 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2673 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2681 /* Enable the iommu */ in iommu_apply_resume_quirks()
2685 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2686 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2687 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2688 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2689 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2694 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2698 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2701 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2702 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2705 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2711 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2712 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2715 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2721 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) in iommu_disable_irtcachedis() argument
2723 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable_irtcachedis()
2726 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) in iommu_enable_irtcachedis() argument
2738 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); in iommu_enable_irtcachedis()
2739 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_enable_irtcachedis()
2742 iommu->irtcachedis_enabled = true; in iommu_enable_irtcachedis()
2743 pr_info("iommu%d (%#06x) : IRT cache is %s\n", in iommu_enable_irtcachedis()
2744 iommu->index, iommu->devid, in iommu_enable_irtcachedis()
2745 iommu->irtcachedis_enabled ? "disabled" : "enabled"); in iommu_enable_irtcachedis()
2748 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2750 iommu_disable(iommu); in early_enable_iommu()
2751 iommu_init_flags(iommu); in early_enable_iommu()
2752 iommu_set_device_table(iommu); in early_enable_iommu()
2753 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2754 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2755 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2756 iommu_enable_gt(iommu); in early_enable_iommu()
2757 iommu_enable_ga(iommu); in early_enable_iommu()
2758 iommu_enable_xt(iommu); in early_enable_iommu()
2759 iommu_enable_irtcachedis(iommu); in early_enable_iommu()
2760 iommu_enable(iommu); in early_enable_iommu()
2761 amd_iommu_flush_all_caches(iommu); in early_enable_iommu()
2774 struct amd_iommu *iommu; in early_enable_iommus() local
2794 for_each_iommu(iommu) { in early_enable_iommus()
2795 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2796 early_enable_iommu(iommu); in early_enable_iommus()
2807 for_each_iommu(iommu) { in early_enable_iommus()
2808 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2809 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2810 iommu_disable_irtcachedis(iommu); in early_enable_iommus()
2811 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2812 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2813 iommu_enable_ga(iommu); in early_enable_iommus()
2814 iommu_enable_xt(iommu); in early_enable_iommus()
2815 iommu_enable_irtcachedis(iommu); in early_enable_iommus()
2816 iommu_set_device_table(iommu); in early_enable_iommus()
2817 amd_iommu_flush_all_caches(iommu); in early_enable_iommus()
2824 struct amd_iommu *iommu; in enable_iommus_ppr() local
2829 for_each_iommu(iommu) in enable_iommus_ppr()
2830 amd_iommu_enable_ppr_log(iommu); in enable_iommus_ppr()
2837 struct amd_iommu *iommu; in enable_iommus_vapic() local
2839 for_each_iommu(iommu) { in enable_iommus_vapic()
2844 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2848 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in enable_iommus_vapic()
2849 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in enable_iommus_vapic()
2856 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2880 for_each_iommu(iommu) { in enable_iommus_vapic()
2881 if (iommu_init_ga_log(iommu) || in enable_iommus_vapic()
2882 iommu_ga_log_enable(iommu)) in enable_iommus_vapic()
2885 iommu_feature_enable(iommu, CONTROL_GAM_EN); in enable_iommus_vapic()
2887 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); in enable_iommus_vapic()
2897 struct amd_iommu *iommu; in disable_iommus() local
2899 for_each_iommu(iommu) in disable_iommus()
2900 iommu_disable(iommu); in disable_iommus()
2915 struct amd_iommu *iommu; in amd_iommu_resume() local
2917 for_each_iommu(iommu) in amd_iommu_resume()
2918 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
2921 for_each_iommu(iommu) in amd_iommu_resume()
2922 early_enable_iommu(iommu); in amd_iommu_resume()
3014 * This is the hardware init function for AMD IOMMU in the system.
3018 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
3143 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
3146 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
3147 ret = iommu_init_irq(iommu); in amd_iommu_enable_interrupts()
3183 /* Don't use IOMMU if there is Stoney Ridge graphics */ in detect_ivrs()
3189 pr_info("Disable IOMMU on Stoney Ridge\n"); in detect_ivrs()
3207 * The SNP support requires that IOMMU must be enabled, and is in iommu_snp_enable()
3211 pr_warn("SNP: IOMMU disabled or configured in passthrough mode, SNP cannot be supported.\n"); in iommu_snp_enable()
3216 pr_warn("SNP: IOMMU is configured with V2 page table mode, SNP cannot be supported.\n"); in iommu_snp_enable()
3222 pr_warn("SNP: IOMMU SNP feature not enabled, SNP cannot be supported.\n"); in iommu_snp_enable()
3227 * Enable host SNP support once SNP support is checked on IOMMU. in iommu_snp_enable()
3234 pr_info("IOMMU SNP support enabled.\n"); in iommu_snp_enable()
3244 * AMD IOMMU Initialization State Machine
3308 struct amd_iommu *iommu; in state_next() local
3314 for_each_iommu(iommu) in state_next()
3315 amd_iommu_flush_all_caches(iommu); in state_next()
3397 * This is the core init function for AMD IOMMU hardware in the system.
3403 struct amd_iommu *iommu; in amd_iommu_init() local
3410 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
3417 for_each_iommu(iommu) in amd_iommu_init()
3418 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
3437 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
3444 * Early detect code. This code runs at IOMMU detection time in the DMA
3465 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
3475 * Parsing functions for the AMD IOMMU specific kernel command line
3509 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); in parse_amd_iommu_options()
3698 /* CPU page table size should match IOMMU guest page table size */ in amd_iommu_pasid_supported()
3714 struct amd_iommu *iommu; in get_amd_iommu() local
3716 for_each_iommu(iommu) in get_amd_iommu()
3718 return iommu; in get_amd_iommu()
3724 * IOMMU EFR Performance Counter support functionality. This code allows
3725 * access to the IOMMU PC functionality.
3731 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3733 if (iommu) in amd_iommu_pc_get_max_banks()
3734 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3746 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3748 if (iommu) in amd_iommu_pc_get_max_counters()
3749 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3754 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3760 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3764 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3765 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3771 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3772 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3780 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3781 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3783 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3785 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3792 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3794 if (!iommu) in amd_iommu_pc_get_reg()
3797 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3800 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3802 if (!iommu) in amd_iommu_pc_set_reg()
3805 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()
3823 pr_warn("IOMMU PFN %lx RMP lookup failed, ret %d\n", pfn, ret); in iommu_page_make_shared()
3828 pr_warn("IOMMU PFN %lx not assigned in RMP table\n", pfn); in iommu_page_make_shared()
3837 pr_warn("PSMASH failed for IOMMU PFN %lx huge RMP entry, ret: %d, level: %d\n", in iommu_page_make_shared()
3866 struct amd_iommu *iommu; in amd_iommu_snp_disable() local
3872 for_each_iommu(iommu) { in amd_iommu_snp_disable()
3873 ret = iommu_make_shared(iommu->evt_buf, EVT_BUFFER_SIZE); in amd_iommu_snp_disable()
3877 ret = iommu_make_shared(iommu->ppr_log, PPR_LOG_SIZE); in amd_iommu_snp_disable()
3881 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); in amd_iommu_snp_disable()