Lines Matching +full:ext +full:- +full:irq +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
19 #include <linux/irq.h>
20 #include <linux/amd-iommu.h>
25 #include <asm/pci-direct.h>
39 #include "../iommu-pages.h"
127 u32 ext;
183 /* IOMMUs have a non-present cache? */
231 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
236 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
243 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
245 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
270 u64 tmp = iommu->features; in get_global_efr()
271 u64 tmp2 = iommu->features2; in get_global_efr()
273 if (list_is_first(&iommu->list, &amd_iommu_list)) { in get_global_efr()
286 iommu->index, iommu->pci_seg->id, in get_global_efr()
287 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), in get_global_efr()
288 PCI_FUNC(iommu->devid)); in get_global_efr()
306 iommu->features = h->efr_reg; in early_iommu_features_init()
307 iommu->features2 = h->efr_reg2; in early_iommu_features_init()
319 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
320 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
326 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
327 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
335 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
336 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
342 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
343 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
356 * This function set the exclusion range in the IOMMU. DMA accesses to the
357 * exclusion range are passed through untranslated
361 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
362 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
365 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
379 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
386 * Re-purpose Exclusion base/limit registers for Completion wait in iommu_set_cwwb_range()
387 * write-back base/limit. in iommu_set_cwwb_range()
389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
396 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
404 u32 dev_table_size = iommu->pci_seg->dev_table_size; in iommu_set_device_table()
407 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
410 entry |= (dev_table_size >> 12) - 1; in iommu_set_device_table()
411 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
420 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
422 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
429 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
431 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
438 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
441 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
452 if (!iommu->mmio_base) in iommu_disable()
484 pr_err("Can not reserve memory region %llx-%llx for mmio\n", in iommu_map_mmio_space()
495 if (iommu->mmio_base) in iommu_unmap_mmio_space()
496 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
497 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
504 switch (h->type) { in get_ivhd_header_size()
530 u32 type = ((struct ivhd_entry *)ivhd)->type; in ivhd_entry_length()
549 int last_devid = -EINVAL; in find_last_devid_from_ivhd()
554 pr_err("Unsupported IVHD type %#x\n", h->type); in find_last_devid_from_ivhd()
555 return -EINVAL; in find_last_devid_from_ivhd()
559 end += h->length; in find_last_devid_from_ivhd()
563 switch (dev->type) { in find_last_devid_from_ivhd()
572 if (dev->devid > last_devid) in find_last_devid_from_ivhd()
573 last_devid = dev->devid; in find_last_devid_from_ivhd()
591 for (i = 0; i < table->length; ++i) in check_ivrs_checksum()
596 return -ENODEV; in check_ivrs_checksum()
615 end += table->length; in find_last_devid_acpi()
618 if (h->pci_seg == pci_seg && in find_last_devid_acpi()
619 h->type == amd_iommu_target_ivhd_type) { in find_last_devid_acpi()
623 return -EINVAL; in find_last_devid_acpi()
627 p += h->length; in find_last_devid_acpi()
646 pci_seg->dev_table = iommu_alloc_pages(GFP_KERNEL | GFP_DMA32, in alloc_dev_table()
647 get_order(pci_seg->dev_table_size)); in alloc_dev_table()
648 if (!pci_seg->dev_table) in alloc_dev_table()
649 return -ENOMEM; in alloc_dev_table()
656 iommu_free_pages(pci_seg->dev_table, in free_dev_table()
657 get_order(pci_seg->dev_table_size)); in free_dev_table()
658 pci_seg->dev_table = NULL; in free_dev_table()
664 pci_seg->rlookup_table = iommu_alloc_pages(GFP_KERNEL, in alloc_rlookup_table()
665 get_order(pci_seg->rlookup_table_size)); in alloc_rlookup_table()
666 if (pci_seg->rlookup_table == NULL) in alloc_rlookup_table()
667 return -ENOMEM; in alloc_rlookup_table()
674 iommu_free_pages(pci_seg->rlookup_table, in free_rlookup_table()
675 get_order(pci_seg->rlookup_table_size)); in free_rlookup_table()
676 pci_seg->rlookup_table = NULL; in free_rlookup_table()
681 pci_seg->irq_lookup_table = iommu_alloc_pages(GFP_KERNEL, in alloc_irq_lookup_table()
682 get_order(pci_seg->rlookup_table_size)); in alloc_irq_lookup_table()
683 kmemleak_alloc(pci_seg->irq_lookup_table, in alloc_irq_lookup_table()
684 pci_seg->rlookup_table_size, 1, GFP_KERNEL); in alloc_irq_lookup_table()
685 if (pci_seg->irq_lookup_table == NULL) in alloc_irq_lookup_table()
686 return -ENOMEM; in alloc_irq_lookup_table()
693 kmemleak_free(pci_seg->irq_lookup_table); in free_irq_lookup_table()
694 iommu_free_pages(pci_seg->irq_lookup_table, in free_irq_lookup_table()
695 get_order(pci_seg->rlookup_table_size)); in free_irq_lookup_table()
696 pci_seg->irq_lookup_table = NULL; in free_irq_lookup_table()
703 pci_seg->alias_table = iommu_alloc_pages(GFP_KERNEL, in alloc_alias_table()
704 get_order(pci_seg->alias_table_size)); in alloc_alias_table()
705 if (!pci_seg->alias_table) in alloc_alias_table()
706 return -ENOMEM; in alloc_alias_table()
711 for (i = 0; i <= pci_seg->last_bdf; ++i) in alloc_alias_table()
712 pci_seg->alias_table[i] = i; in alloc_alias_table()
719 iommu_free_pages(pci_seg->alias_table, in free_alias_table()
720 get_order(pci_seg->alias_table_size)); in free_alias_table()
721 pci_seg->alias_table = NULL; in free_alias_table()
731 iommu->cmd_buf = iommu_alloc_pages(GFP_KERNEL, in alloc_command_buffer()
734 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
747 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
756 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
792 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
793 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
794 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
795 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
808 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
810 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
813 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
829 iommu_free_pages(iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
851 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL, in alloc_event_buffer()
854 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
861 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
863 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
865 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
869 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
870 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
885 iommu_free_pages(iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
891 iommu_free_pages(iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
892 iommu_free_pages(iommu->ga_log_tail, get_order(8)); in free_ga_log()
902 if (!iommu->ga_log) in iommu_ga_log_enable()
903 return -EINVAL; in iommu_ga_log_enable()
905 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_ga_log_enable()
906 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_ga_log_enable()
908 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_ga_log_enable()
909 (BIT_ULL(52)-1)) & ~7ULL; in iommu_ga_log_enable()
910 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_ga_log_enable()
912 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_ga_log_enable()
913 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_ga_log_enable()
920 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
927 return -EINVAL; in iommu_ga_log_enable()
937 iommu->ga_log = iommu_alloc_pages(GFP_KERNEL, get_order(GA_LOG_SIZE)); in iommu_init_ga_log()
938 if (!iommu->ga_log) in iommu_init_ga_log()
941 iommu->ga_log_tail = iommu_alloc_pages(GFP_KERNEL, get_order(8)); in iommu_init_ga_log()
942 if (!iommu->ga_log_tail) in iommu_init_ga_log()
948 return -EINVAL; in iommu_init_ga_log()
954 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); in alloc_cwwb_sem()
956 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
961 if (iommu->cmd_sem) in free_cwwb_sem()
962 iommu_free_page((void *)iommu->cmd_sem); in free_cwwb_sem()
969 * XT mode (32-bit APIC destination ID) requires in iommu_enable_xt()
970 * GA mode (128-bit IRTE support) as a prerequisite. in iommu_enable_xt()
992 dte->data[i] |= (1UL << _bit); in set_dte_bit()
998 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in __copy_device_table()
1006 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in __copy_device_table()
1007 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in __copy_device_table()
1011 if (old_devtb_size != pci_seg->dev_table_size) { in __copy_device_table()
1013 iommu->index); in __copy_device_table()
1030 pci_seg->dev_table_size) in __copy_device_table()
1031 : memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB); in __copy_device_table()
1036 pci_seg->old_dev_tbl_cpy = iommu_alloc_pages(GFP_KERNEL | GFP_DMA32, in __copy_device_table()
1037 get_order(pci_seg->dev_table_size)); in __copy_device_table()
1038 if (pci_seg->old_dev_tbl_cpy == NULL) { in __copy_device_table()
1044 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { in __copy_device_table()
1045 pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid]; in __copy_device_table()
1050 pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; in __copy_device_table()
1051 pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; in __copy_device_table()
1061 pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp; in __copy_device_table()
1063 pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp; in __copy_device_table()
1073 pr_err("Wrong old irq remapping flag: %#x\n", devid); in __copy_device_table()
1078 pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; in __copy_device_table()
1094 pr_warn("Translation is already enabled - trying to copy translation structures\n"); in copy_device_table()
1102 if (pci_seg->id != iommu->pci_seg->id) in copy_device_table()
1121 * Need to go through the whole list to find the smallest range, in amd_iommu_get_ivhd_dte_flags()
1124 if ((e->segid == segid) && in amd_iommu_get_ivhd_dte_flags()
1125 (e->devid_first <= devid) && (devid <= e->devid_last)) { in amd_iommu_get_ivhd_dte_flags()
1126 unsigned int len = e->devid_last - e->devid_first; in amd_iommu_get_ivhd_dte_flags()
1129 dte = &(e->dte); in amd_iommu_get_ivhd_dte_flags()
1142 if ((e->segid == segid) && in search_ivhd_dte_flags()
1143 (e->devid_first == first) && in search_ivhd_dte_flags()
1144 (e->devid_last == last)) in search_ivhd_dte_flags()
1165 if (search_ivhd_dte_flags(iommu->pci_seg->id, first, last)) in set_dev_entry_from_acpi_range()
1172 pr_debug("%s: devid range %#x:%#x\n", __func__, first, last); in set_dev_entry_from_acpi_range()
1193 memcpy(&d->dte, &dte, sizeof(dte)); in set_dev_entry_from_acpi_range()
1194 d->segid = iommu->pci_seg->id; in set_dev_entry_from_acpi_range()
1195 d->devid_first = first; in set_dev_entry_from_acpi_range()
1196 d->devid_last = last; in set_dev_entry_from_acpi_range()
1197 list_add_tail(&d->list, &amd_ivhd_dev_flags_list); in set_dev_entry_from_acpi_range()
1226 return -EINVAL; in add_special_device()
1229 if (!(entry->id == id && entry->cmd_line)) in add_special_device()
1232 pr_info("Command-line override present for %s id %d - ignoring\n", in add_special_device()
1235 *devid = entry->devid; in add_special_device()
1242 return -ENOMEM; in add_special_device()
1244 entry->id = id; in add_special_device()
1245 entry->devid = *devid; in add_special_device()
1246 entry->cmd_line = cmd_line; in add_special_device()
1248 list_add_tail(&entry->list, list); in add_special_device()
1260 if (strcmp(entry->hid, hid) || in add_acpi_hid_device()
1261 (*uid && *entry->uid && strcmp(entry->uid, uid)) || in add_acpi_hid_device()
1262 !entry->cmd_line) in add_acpi_hid_device()
1265 pr_info("Command-line override for hid:%s uid:%s\n", in add_acpi_hid_device()
1267 *devid = entry->devid; in add_acpi_hid_device()
1273 return -ENOMEM; in add_acpi_hid_device()
1275 memcpy(entry->uid, uid, strlen(uid)); in add_acpi_hid_device()
1276 memcpy(entry->hid, hid, strlen(hid)); in add_acpi_hid_device()
1277 entry->devid = *devid; in add_acpi_hid_device()
1278 entry->cmd_line = cmd_line; in add_acpi_hid_device()
1279 entry->root_devid = (entry->devid & (~0x7)); in add_acpi_hid_device()
1282 entry->cmd_line ? "cmd" : "ivrs", in add_acpi_hid_device()
1283 entry->hid, entry->uid, entry->root_devid); in add_acpi_hid_device()
1285 list_add_tail(&entry->list, list); in add_acpi_hid_device()
1336 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in init_iommu_from_acpi()
1350 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1357 pr_err("Unsupported IVHD type %#x\n", h->type); in init_iommu_from_acpi()
1358 return -EINVAL; in init_iommu_from_acpi()
1363 end += h->length; in init_iommu_from_acpi()
1368 seg_id = pci_seg->id; in init_iommu_from_acpi()
1370 switch (e->type) { in init_iommu_from_acpi()
1373 DUMP_printk(" DEV_ALL\t\t\tsetting: %#02x\n", e->flags); in init_iommu_from_acpi()
1374 set_dev_entry_from_acpi_range(iommu, 0, pci_seg->last_bdf, e->flags, 0); in init_iommu_from_acpi()
1379 seg_id, PCI_BUS_NUM(e->devid), in init_iommu_from_acpi()
1380 PCI_SLOT(e->devid), in init_iommu_from_acpi()
1381 PCI_FUNC(e->devid), in init_iommu_from_acpi()
1382 e->flags); in init_iommu_from_acpi()
1384 devid = e->devid; in init_iommu_from_acpi()
1385 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1390 seg_id, PCI_BUS_NUM(e->devid), in init_iommu_from_acpi()
1391 PCI_SLOT(e->devid), in init_iommu_from_acpi()
1392 PCI_FUNC(e->devid), in init_iommu_from_acpi()
1393 e->flags); in init_iommu_from_acpi()
1395 devid_start = e->devid; in init_iommu_from_acpi()
1396 flags = e->flags; in init_iommu_from_acpi()
1403 seg_id, PCI_BUS_NUM(e->devid), in init_iommu_from_acpi()
1404 PCI_SLOT(e->devid), in init_iommu_from_acpi()
1405 PCI_FUNC(e->devid), in init_iommu_from_acpi()
1406 e->flags, in init_iommu_from_acpi()
1407 PCI_BUS_NUM(e->ext >> 8), in init_iommu_from_acpi()
1408 PCI_SLOT(e->ext >> 8), in init_iommu_from_acpi()
1409 PCI_FUNC(e->ext >> 8)); in init_iommu_from_acpi()
1411 devid = e->devid; in init_iommu_from_acpi()
1412 devid_to = e->ext >> 8; in init_iommu_from_acpi()
1413 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1414 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1415 pci_seg->alias_table[devid] = devid_to; in init_iommu_from_acpi()
1420 seg_id, PCI_BUS_NUM(e->devid), in init_iommu_from_acpi()
1421 PCI_SLOT(e->devid), in init_iommu_from_acpi()
1422 PCI_FUNC(e->devid), in init_iommu_from_acpi()
1423 e->flags, in init_iommu_from_acpi()
1424 seg_id, PCI_BUS_NUM(e->ext >> 8), in init_iommu_from_acpi()
1425 PCI_SLOT(e->ext >> 8), in init_iommu_from_acpi()
1426 PCI_FUNC(e->ext >> 8)); in init_iommu_from_acpi()
1428 devid_start = e->devid; in init_iommu_from_acpi()
1429 flags = e->flags; in init_iommu_from_acpi()
1430 devid_to = e->ext >> 8; in init_iommu_from_acpi()
1436 DUMP_printk(" DEV_EXT_SELECT\t\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", in init_iommu_from_acpi()
1437 seg_id, PCI_BUS_NUM(e->devid), in init_iommu_from_acpi()
1438 PCI_SLOT(e->devid), in init_iommu_from_acpi()
1439 PCI_FUNC(e->devid), in init_iommu_from_acpi()
1440 e->flags, e->ext); in init_iommu_from_acpi()
1442 devid = e->devid; in init_iommu_from_acpi()
1443 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1444 e->ext); in init_iommu_from_acpi()
1448 DUMP_printk(" DEV_EXT_SELECT_RANGE\tdevid: %04x:%02x:%02x.%x flags: %#02x ext: %08x\n", in init_iommu_from_acpi()
1449 seg_id, PCI_BUS_NUM(e->devid), in init_iommu_from_acpi()
1450 PCI_SLOT(e->devid), in init_iommu_from_acpi()
1451 PCI_FUNC(e->devid), in init_iommu_from_acpi()
1452 e->flags, e->ext); in init_iommu_from_acpi()
1454 devid_start = e->devid; in init_iommu_from_acpi()
1455 flags = e->flags; in init_iommu_from_acpi()
1456 ext_flags = e->ext; in init_iommu_from_acpi()
1462 seg_id, PCI_BUS_NUM(e->devid), in init_iommu_from_acpi()
1463 PCI_SLOT(e->devid), in init_iommu_from_acpi()
1464 PCI_FUNC(e->devid)); in init_iommu_from_acpi()
1466 devid = e->devid; in init_iommu_from_acpi()
1469 pci_seg->alias_table[dev_i] = devid_to; in init_iommu_from_acpi()
1480 handle = e->ext & 0xff; in init_iommu_from_acpi()
1481 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, (e->ext >> 8)); in init_iommu_from_acpi()
1482 type = (e->ext >> 24) & 0xff; in init_iommu_from_acpi()
1496 e->flags); in init_iommu_from_acpi()
1504 * command-line override is present. So call in init_iommu_from_acpi()
1507 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1517 if (h->type != 0x40) { in init_iommu_from_acpi()
1519 e->type); in init_iommu_from_acpi()
1523 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); in init_iommu_from_acpi()
1524 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); in init_iommu_from_acpi()
1525 hid[ACPIHID_HID_LEN - 1] = '\0'; in init_iommu_from_acpi()
1533 switch (e->uidf) { in init_iommu_from_acpi()
1536 if (e->uidl != 0) in init_iommu_from_acpi()
1542 sprintf(uid, "%d", e->uid); in init_iommu_from_acpi()
1547 memcpy(uid, &e->uid, e->uidl); in init_iommu_from_acpi()
1548 uid[e->uidl] = '\0'; in init_iommu_from_acpi()
1555 devid = PCI_SEG_DEVID_TO_SBDF(seg_id, e->devid); in init_iommu_from_acpi()
1561 e->flags); in init_iommu_from_acpi()
1563 flags = e->flags; in init_iommu_from_acpi()
1571 * command-line override is present. So call in init_iommu_from_acpi()
1574 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1608 pci_seg->last_bdf = last_bdf; in alloc_pci_segment()
1610 pci_seg->dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE, last_bdf); in alloc_pci_segment()
1611 pci_seg->alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE, last_bdf); in alloc_pci_segment()
1612 pci_seg->rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE, last_bdf); in alloc_pci_segment()
1614 pci_seg->id = id; in alloc_pci_segment()
1615 init_llist_head(&pci_seg->dev_data_list); in alloc_pci_segment()
1616 INIT_LIST_HEAD(&pci_seg->unity_map); in alloc_pci_segment()
1617 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); in alloc_pci_segment()
1635 if (pci_seg->id == id) in get_pci_segment()
1647 list_del(&pci_seg->list); in free_pci_segments()
1658 if (iommu->iommu.dev) { in free_sysfs()
1659 iommu_device_unregister(&iommu->iommu); in free_sysfs()
1660 iommu_device_sysfs_remove(&iommu->iommu); in free_sysfs()
1681 list_del(&iommu->list); in free_iommu_all()
1688 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1702 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1703 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1709 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1711 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1712 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1715 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1719 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1742 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1755 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); in init_iommu_one()
1757 return -ENOMEM; in init_iommu_one()
1758 iommu->pci_seg = pci_seg; in init_iommu_one()
1760 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1761 atomic64_set(&iommu->cmd_sem_val, 0); in init_iommu_one()
1764 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1765 iommu->index = amd_iommus_present++; in init_iommu_one()
1767 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1769 return -ENOSYS; in init_iommu_one()
1775 iommu->devid = h->devid; in init_iommu_one()
1776 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1777 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1779 switch (h->type) { in init_iommu_one()
1782 if ((h->efr_attr != 0) && in init_iommu_one()
1783 ((h->efr_attr & (0xF << 13)) != 0) && in init_iommu_one()
1784 ((h->efr_attr & (0x3F << 17)) != 0)) in init_iommu_one()
1785 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1787 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1790 if ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0) in init_iommu_one()
1795 if (h->efr_reg & (1 << 9)) in init_iommu_one()
1796 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1798 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1801 if ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0) { in init_iommu_one()
1806 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) in init_iommu_one()
1813 return -EINVAL; in init_iommu_one()
1816 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1817 iommu->mmio_phys_end); in init_iommu_one()
1818 if (!iommu->mmio_base) in init_iommu_one()
1819 return -ENOMEM; in init_iommu_one()
1829 return -ENOMEM; in init_iommu_one_late()
1832 return -ENOMEM; in init_iommu_one_late()
1835 return -ENOMEM; in init_iommu_one_late()
1837 iommu->int_enabled = false; in init_iommu_one_late()
1844 iommu->index); in init_iommu_one_late()
1859 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; in init_iommu_one_late()
1865 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1875 u8 last_type = ivhd->type; in get_highest_supported_ivhd_type()
1876 u16 devid = ivhd->devid; in get_highest_supported_ivhd_type()
1878 while (((u8 *)ivhd - base < ivrs->length) && in get_highest_supported_ivhd_type()
1879 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { in get_highest_supported_ivhd_type()
1882 if (ivhd->devid == devid) in get_highest_supported_ivhd_type()
1883 last_type = ivhd->type; in get_highest_supported_ivhd_type()
1884 ivhd = (struct ivhd_header *)(p + ivhd->length); in get_highest_supported_ivhd_type()
1901 end += table->length; in init_iommu_all()
1911 h->pci_seg, PCI_BUS_NUM(h->devid), in init_iommu_all()
1912 PCI_SLOT(h->devid), PCI_FUNC(h->devid), in init_iommu_all()
1913 h->cap_ptr, h->flags, h->info); in init_iommu_all()
1914 DUMP_printk(" mmio-addr: %016llx\n", in init_iommu_all()
1915 h->mmio_phys); in init_iommu_all()
1919 return -ENOMEM; in init_iommu_all()
1925 p += h->length; in init_iommu_all()
1946 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1955 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1956 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1957 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1967 return sysfs_emit(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1986 .name = "amd-iommu",
2004 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
2008 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
2009 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); in late_iommu_features_init()
2032 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
2035 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2036 PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
2037 iommu->devid & 0xff); in iommu_init_pci()
2038 if (!iommu->dev) in iommu_init_pci()
2039 return -ENODEV; in iommu_init_pci()
2042 iommu->dev->match_driver = false; in iommu_init_pci()
2044 /* ACPI _PRT won't have an IRQ for IOMMU */ in iommu_init_pci()
2045 iommu->dev->irq_managed = 1; in iommu_init_pci()
2047 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
2048 &iommu->cap); in iommu_init_pci()
2050 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
2060 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; in iommu_init_pci()
2062 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); in iommu_init_pci()
2066 if (amd_iommu_max_glx_val == -1) in iommu_init_pci()
2075 return -ENOMEM; in iommu_init_pci()
2077 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { in iommu_init_pci()
2085 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
2088 iommu->root_pdev = in iommu_init_pci()
2089 pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2090 iommu->dev->bus->number, in iommu_init_pci()
2098 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
2099 &iommu->stored_addr_lo); in iommu_init_pci()
2100 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
2101 &iommu->stored_addr_hi); in iommu_init_pci()
2104 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
2108 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
2111 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
2117 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
2118 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
2132 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); in iommu_init_pci()
2134 return pci_enable_device(iommu->dev); in iommu_init_pci()
2186 iommu->index, ret); in amd_iommu_init_pci()
2189 /* Need to setup range after PCI init */ in amd_iommu_init_pci()
2228 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
2232 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
2235 0, "AMD-Vi", in iommu_setup_msi()
2239 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2280 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) in intcapxt_irqdomain_alloc()
2281 return -EINVAL; in intcapxt_irqdomain_alloc()
2290 irqd->chip = &intcapxt_controller; in intcapxt_irqdomain_alloc()
2291 irqd->hwirq = info->hwirq; in intcapxt_irqdomain_alloc()
2292 irqd->chip_data = info->data; in intcapxt_irqdomain_alloc()
2308 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_unmask_irq()
2313 xt.dest_mode_logical = apic->dest_mode_logical; in intcapxt_unmask_irq()
2314 xt.vector = cfg->vector; in intcapxt_unmask_irq()
2315 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); in intcapxt_unmask_irq()
2316 xt.destid_24_31 = cfg->dest_apicid >> 24; in intcapxt_unmask_irq()
2318 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); in intcapxt_unmask_irq()
2323 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_mask_irq()
2325 writeq(0, iommu->mmio_base + irqd->hwirq); in intcapxt_mask_irq()
2332 struct irq_data *parent = irqd->parent_data; in intcapxt_set_affinity()
2335 ret = parent->chip->irq_set_affinity(parent, mask, force); in intcapxt_set_affinity()
2343 return on ? -EOPNOTSUPP : 0; in intcapxt_set_wake()
2347 .name = "IOMMU-MSI",
2371 /* No need for locking here (yet) as the init is single-threaded */ in iommu_get_irqdomain()
2375 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); in iommu_get_irqdomain()
2393 int irq, ret; in __iommu_setup_intcapxt() local
2394 int node = dev_to_node(&iommu->dev->dev); in __iommu_setup_intcapxt()
2398 return -ENXIO; in __iommu_setup_intcapxt()
2405 irq = irq_domain_alloc_irqs(domain, 1, node, &info); in __iommu_setup_intcapxt()
2406 if (irq < 0) { in __iommu_setup_intcapxt()
2408 return irq; in __iommu_setup_intcapxt()
2411 ret = request_threaded_irq(irq, amd_iommu_int_handler, in __iommu_setup_intcapxt()
2414 irq_domain_free_irqs(irq, 1); in __iommu_setup_intcapxt()
2426 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), in iommu_setup_intcapxt()
2427 "AMD-Vi%d-Evt", iommu->index); in iommu_setup_intcapxt()
2428 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, in iommu_setup_intcapxt()
2434 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), in iommu_setup_intcapxt()
2435 "AMD-Vi%d-PPR", iommu->index); in iommu_setup_intcapxt()
2436 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, in iommu_setup_intcapxt()
2443 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), in iommu_setup_intcapxt()
2444 "AMD-Vi%d-GA", iommu->index); in iommu_setup_intcapxt()
2445 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, in iommu_setup_intcapxt()
2457 if (iommu->int_enabled) in iommu_init_irq()
2462 else if (iommu->dev->msi_cap) in iommu_init_irq()
2465 ret = -ENODEV; in iommu_init_irq()
2470 iommu->int_enabled = true; in iommu_init_irq()
2495 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { in free_unity_maps()
2496 list_del(&entry->list); in free_unity_maps()
2510 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); in init_unity_map_range()
2512 return -ENOMEM; in init_unity_map_range()
2516 return -ENOMEM; in init_unity_map_range()
2518 switch (m->type) { in init_unity_map_range()
2524 e->devid_start = e->devid_end = m->devid; in init_unity_map_range()
2528 e->devid_start = 0; in init_unity_map_range()
2529 e->devid_end = pci_seg->last_bdf; in init_unity_map_range()
2533 e->devid_start = m->devid; in init_unity_map_range()
2534 e->devid_end = m->aux; in init_unity_map_range()
2537 e->address_start = PAGE_ALIGN(m->range_start); in init_unity_map_range()
2538 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); in init_unity_map_range()
2539 e->prot = m->flags >> 1; in init_unity_map_range()
2542 * Treat per-device exclusion ranges as r/w unity-mapped regions in init_unity_map_range()
2544 * range (exclusion_start and exclusion_length members). This in init_unity_map_range()
2548 if (m->flags & IVMD_FLAG_EXCL_RANGE) in init_unity_map_range()
2549 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; in init_unity_map_range()
2553 " flags: %x\n", s, m->pci_seg, in init_unity_map_range()
2554 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), in init_unity_map_range()
2555 PCI_FUNC(e->devid_start), m->pci_seg, in init_unity_map_range()
2556 PCI_BUS_NUM(e->devid_end), in init_unity_map_range()
2557 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), in init_unity_map_range()
2558 e->address_start, e->address_end, m->flags); in init_unity_map_range()
2560 list_add_tail(&e->list, &pci_seg->unity_map); in init_unity_map_range()
2571 end += table->length; in init_memory_definitions()
2576 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) in init_memory_definitions()
2579 p += m->length; in init_memory_definitions()
2591 struct dev_table_entry *dev_table = pci_seg->dev_table; in init_device_table_dma()
2596 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { in init_device_table_dma()
2606 struct dev_table_entry *dev_table = pci_seg->dev_table; in uninit_device_table_dma()
2611 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) { in uninit_device_table_dma()
2626 for (devid = 0; devid <= pci_seg->last_bdf; ++devid) in init_device_table()
2627 set_dte_bit(&pci_seg->dev_table[devid], DEV_ENTRY_IRQ_TBL_EN); in init_device_table()
2633 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2637 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2641 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2645 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2666 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2669 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2686 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2687 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2688 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2689 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2694 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2698 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2701 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2702 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2712 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2715 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2739 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_enable_irtcachedis()
2742 iommu->irtcachedis_enabled = true; in iommu_enable_irtcachedis()
2744 iommu->index, iommu->devid, in iommu_enable_irtcachedis()
2745 iommu->irtcachedis_enabled ? "disabled" : "enabled"); in iommu_enable_irtcachedis()
2768 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2787 if (pci_seg->old_dev_tbl_cpy != NULL) { in early_enable_iommus()
2788 iommu_free_pages(pci_seg->old_dev_tbl_cpy, in early_enable_iommus()
2789 get_order(pci_seg->dev_table_size)); in early_enable_iommus()
2790 pci_seg->old_dev_tbl_cpy = NULL; in early_enable_iommus()
2802 iommu_free_pages(pci_seg->dev_table, in early_enable_iommus()
2803 get_order(pci_seg->dev_table_size)); in early_enable_iommus()
2804 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; in early_enable_iommus()
2844 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2856 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2920 /* re-load the hardware */ in amd_iommu_resume()
2964 * anymore - so be careful in check_ioapic_information()
3047 return -ENODEV; in early_amd_iommu_init()
3051 return -ENODEV; in early_amd_iommu_init()
3055 return -EINVAL; in early_amd_iommu_init()
3060 return -EINVAL; in early_amd_iommu_init()
3091 pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); in early_amd_iommu_init()
3109 ret = -ENOMEM; in early_amd_iommu_init()
3256 ret = -ENODEV; in state_next()
3264 ret = -EINVAL; in state_next()
3295 ret = -EINVAL; in state_next()
3323 int ret = -EINVAL; in iommu_go_to_state()
3338 * in IOMMUs, then the system is in a half-baked state, but can limp in iommu_go_to_state()
3339 * along as all memory should be Hypervisor-Owned in the RMP. WARN, in iommu_go_to_state()
3362 return amd_iommu_irq_remap ? 0 : -ENODEV; in amd_iommu_prepare()
3410 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
3505 return -EINVAL; in parse_amd_iommu_options()
3524 pr_info("Restricting V1 page-sizes to 4KiB"); in parse_amd_iommu_options()
3527 pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB"); in parse_amd_iommu_options()
3530 pr_notice("Unknown option - '%s'\n", str); in parse_amd_iommu_options()
3563 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", in parse_ivrs_ioapic()
3601 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", in parse_ivrs_hpet()
3704 * Since DTE[Mode]=0 is prohibited on SNP-enabled system in amd_iommu_pasid_supported()
3734 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3749 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3762 return -ENODEV; in iommu_pc_get_set_reg()
3766 return -ENODEV; in iommu_pc_get_set_reg()
3771 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3772 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3775 return -EINVAL; in iommu_pc_get_set_reg()
3780 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3781 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3783 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3785 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3795 return -EINVAL; in amd_iommu_pc_get_reg()
3803 return -EINVAL; in amd_iommu_pc_set_reg()
3829 return -EINVAL; in iommu_page_make_shared()
3873 ret = iommu_make_shared(iommu->evt_buf, EVT_BUFFER_SIZE); in amd_iommu_snp_disable()
3877 ret = iommu_make_shared(iommu->ppr_log, PPR_LOG_SIZE); in amd_iommu_snp_disable()
3881 ret = iommu_make_shared((void *)iommu->cmd_sem, PAGE_SIZE); in amd_iommu_snp_disable()