Lines Matching +full:0 +full:xb000
25 #define IQS7222_PROD_NUM 0x00
31 #define IQS7222_SYS_STATUS 0x10
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
48 #define IQS7222_SYS_SETUP 0xD0
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
63 #define IQS7222_COMMS_HOLD BIT(0)
64 #define IQS7222_COMMS_ERROR 0xEEEE
85 #define IQS7222_REG_OFFSET 0x100
165 .mask = BIT(0),
166 .val = BIT(0),
167 .enable = BIT(0),
207 .link = BIT(0),
208 .mask = BIT(0),
209 .val = BIT(0),
210 .enable = BIT(0),
325 .base = 0x8000,
330 .base = 0x8700,
335 .base = 0x9000,
340 .base = 0xA000,
345 .base = 0xAC00,
351 .base = 0xB000,
356 .base = 0xC000,
384 .base = 0x8000,
389 .base = 0x8700,
394 .base = 0x9000,
399 .base = 0xA000,
404 .base = 0xAC00,
410 .base = 0xB000,
415 .base = 0xC000,
439 .base = 0x8000,
444 .base = 0x8A00,
449 .base = 0x9000,
454 .base = 0xB000,
459 .base = 0xC400,
482 .base = 0x8000,
487 .base = 0x8A00,
492 .base = 0x9000,
497 .base = 0xB000,
502 .base = 0xC400,
530 .base = 0x8000,
535 .base = 0x8500,
540 .base = 0x9000,
545 .base = 0xA000,
550 .base = 0xAA00,
556 .base = 0xB000,
561 .base = 0xC000,
588 .base = 0x8000,
593 .base = 0x8500,
598 .base = 0x9000,
603 .base = 0xA000,
608 .base = 0xAA00,
614 .base = 0xB000,
619 .base = 0xC000,
645 .base = 0x8000,
650 .base = 0x8700,
655 .base = 0x9000,
660 .base = 0xA000,
665 .base = 0xAE00,
671 .base = 0xB000,
676 .base = 0xC000,
702 .base = 0x8000,
707 .base = 0x8700,
712 .base = 0x9000,
717 .base = 0xA000,
722 .base = 0xAE00,
728 .base = 0xB000,
733 .base = 0xC000,
746 .fw_major = 0,
759 .base = 0x8000,
764 .base = 0x8700,
769 .base = 0x9000,
774 .base = 0xA000,
779 .base = 0xAE00,
785 .base = 0xB000,
790 .base = 0xC000,
821 .reg_offset = 0,
829 .reg_offset = 0,
830 .reg_shift = 0,
867 .reg_shift = 0,
891 .reg_shift = 0,
898 .reg_offset = 0,
906 .reg_offset = 0,
923 .reg_shift = 0,
931 .reg_shift = 0,
938 .reg_offset = 0,
946 .reg_offset = 0,
953 .reg_offset = 0,
960 .reg_offset = 0,
967 .reg_offset = 0,
974 .reg_offset = 0,
981 .reg_offset = 0,
982 .reg_shift = 0,
1008 .reg_shift = 0,
1033 .reg_shift = 0,
1049 .reg_shift = 0,
1057 .reg_offset = 0,
1066 .reg_offset = 0,
1075 .reg_offset = 0,
1076 .reg_shift = 0,
1086 .reg_shift = 0,
1102 .reg_offset = 0,
1110 .reg_offset = 0,
1118 .reg_offset = 0,
1126 .reg_offset = 0,
1127 .reg_shift = 0,
1143 .reg_shift = 0,
1150 .reg_offset = 0,
1159 .reg_offset = 0,
1167 .reg_offset = 0,
1176 .reg_offset = 0,
1184 .reg_offset = 0,
1201 .reg_shift = 0,
1270 .reg_shift = 0,
1280 .reg_shift = 0,
1288 .reg_offset = 0,
1298 .reg_offset = 0,
1299 .reg_shift = 0,
1317 .reg_shift = 0,
1333 .reg_shift = 0,
1350 .reg_shift = 0,
1379 .reg_shift = 0,
1389 .reg_shift = 0,
1398 .reg_shift = 0,
1405 .reg_offset = 0,
1413 .reg_shift = 0,
1422 .reg_shift = 0,
1430 .reg_shift = 0,
1438 .reg_shift = 0,
1447 .reg_shift = 0,
1455 .reg_shift = 0,
1464 .reg_shift = 0,
1472 .reg_shift = 0,
1547 if (ret < 0) in iqs7222_irq_poll()
1549 else if (ret > 0) in iqs7222_irq_poll()
1550 return 0; in iqs7222_irq_poll()
1551 } while (ktime_compare(ktime_get(), irq_timeout) < 0); in iqs7222_irq_poll()
1562 return 0; in iqs7222_hard_reset()
1567 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0); in iqs7222_hard_reset()
1578 u8 msg_buf[] = { 0xFF, }; in iqs7222_force_comms()
1584 * ever all write data is ignored, and all read data returns 0xEE. in iqs7222_force_comms()
1595 if (ret < 0) in iqs7222_force_comms()
1597 else if (ret > 0) in iqs7222_force_comms()
1598 return 0; in iqs7222_force_comms()
1602 if (ret >= 0) in iqs7222_force_comms()
1625 .flags = 0, in iqs7222_read_burst()
1647 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_read_burst()
1649 if (ret < 0) in iqs7222_read_burst()
1654 if (ret >= 0) in iqs7222_read_burst()
1666 ret = 0; in iqs7222_read_burst()
1676 if (ret < 0) in iqs7222_read_burst()
1678 "Failed to read from address 0x%04X: %d\n", reg, ret); in iqs7222_read_burst()
1694 return 0; in iqs7222_read_word()
1726 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_write_burst()
1728 if (ret < 0) in iqs7222_write_burst()
1733 if (ret >= 0) in iqs7222_write_burst()
1740 ret = 0; in iqs7222_write_burst()
1748 if (ret < 0) in iqs7222_write_burst()
1750 "Failed to write to address 0x%04X: %d\n", reg, ret); in iqs7222_write_burst()
1766 u16 sys_status = 0; in iqs7222_ati_trigger()
1780 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_ati_trigger()
1805 return 0; in iqs7222_ati_trigger()
1824 } while (ktime_compare(ktime_get(), ati_timeout) < 0); in iqs7222_ati_trigger()
1827 "ATI attempt %d of %d failed with status 0x%02X, %s\n", in iqs7222_ati_trigger()
1847 iqs7222->sys_setup[0] | in iqs7222_dev_init()
1874 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { in iqs7222_dev_init()
1885 val = iqs7222_setup(iqs7222, i, 0); in iqs7222_dev_init()
1893 for (j = 0; j < num_row; j++) { in iqs7222_dev_init()
1898 for (k = 0; k < num_col; k++) in iqs7222_dev_init()
1903 for (k = 0; k < num_col; k++) in iqs7222_dev_init()
1943 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK; in iqs7222_dev_init()
1944 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK; in iqs7222_dev_init()
1945 return 0; in iqs7222_dev_init()
1963 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) { in iqs7222_dev_info()
1964 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num) in iqs7222_dev_info()
1976 return 0; in iqs7222_dev_info()
1984 le16_to_cpu(dev_id[0])); in iqs7222_dev_info()
2000 return 0; in iqs7222_gpio_select()
2003 return 0; in iqs7222_gpio_select()
2010 } else if (count < 0) { in iqs7222_gpio_select()
2025 for (i = 0; i < count; i++) { in iqs7222_gpio_select()
2043 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN; in iqs7222_gpio_select()
2048 return 0; in iqs7222_gpio_select()
2062 return 0; in iqs7222_parse_props()
2064 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) { in iqs7222_parse_props()
2116 val_max = GENMASK(reg_width - 1, 0) * val_pitch; in iqs7222_parse_props()
2129 return 0; in iqs7222_parse_props()
2156 return 0; in iqs7222_parse_event()
2165 return 0; in iqs7222_parse_event()
2184 return 0; in iqs7222_parse_event()
2205 return 0; in iqs7222_parse_cycle()
2208 if (count < 0) { in iqs7222_parse_cycle()
2228 for (i = 0; i < count; i++) { in iqs7222_parse_cycle()
2238 return 0; in iqs7222_parse_cycle()
2257 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN; in iqs7222_parse_chan()
2289 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW; in iqs7222_parse_chan()
2314 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; in iqs7222_parse_chan()
2327 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; in iqs7222_parse_chan()
2341 if (count < 0) { in iqs7222_parse_chan()
2363 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4); in iqs7222_parse_chan()
2365 for (i = 0; i < count; i++) { in iqs7222_parse_chan()
2366 int min_crx = chan_index < ext_chan / 2 ? 0 : 4; in iqs7222_parse_chan()
2375 chan_setup[0] |= BIT(pins[i] + 4 - min_crx); in iqs7222_parse_chan()
2379 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) { in iqs7222_parse_chan()
2421 dev_desc->touch_link - (i ? 0 : 2), in iqs7222_parse_chan()
2460 if (count < 0) { in iqs7222_parse_sldr()
2484 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1; in iqs7222_parse_sldr()
2486 sldr_setup[0] |= count; in iqs7222_parse_sldr()
2487 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0); in iqs7222_parse_sldr()
2489 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { in iqs7222_parse_sldr()
2490 sldr_setup[5 + reg_offset + i] = 0; in iqs7222_parse_sldr()
2573 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0); in iqs7222_parse_sldr()
2582 sldr_setup[0] &= ~dev_desc->wheel_enable; in iqs7222_parse_sldr()
2584 sldr_setup[0] |= dev_desc->wheel_enable; in iqs7222_parse_sldr()
2593 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) in iqs7222_parse_sldr()
2596 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) { in iqs7222_parse_sldr()
2644 * coordinate field reports 0xFFFF and solely relies on touch in iqs7222_parse_sldr()
2685 if (count < 0) { in iqs7222_parse_tpad()
2704 tpad_setup[6] &= ~GENMASK(num_chan - 1, 0); in iqs7222_parse_tpad()
2706 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { in iqs7222_parse_tpad()
2707 tpad_setup[8 + i] = 0; in iqs7222_parse_tpad()
2729 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) in iqs7222_parse_tpad()
2733 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) { in iqs7222_parse_tpad()
2761 * coordinate fields report 0xFFFF and solely relies on touch in iqs7222_parse_tpad()
2772 if (!iqs7222->tp_code[0]) in iqs7222_parse_tpad()
2773 return 0; in iqs7222_parse_tpad()
2776 0, (tpad_setup[4] ? : 1) - 1, 0, 0); in iqs7222_parse_tpad()
2779 0, (tpad_setup[5] ? : 1) - 1, 0, 0); in iqs7222_parse_tpad()
2792 return 0; in iqs7222_parse_tpad()
2826 return 0; in iqs7222_parse_reg_grp()
2840 return 0; in iqs7222_parse_reg_grp()
2856 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) { in iqs7222_parse_all()
2859 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN; in iqs7222_parse_all()
2860 gpio_setup[1] = 0; in iqs7222_parse_all()
2861 gpio_setup[2] = 0; in iqs7222_parse_all()
2870 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++) in iqs7222_parse_all()
2871 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]); in iqs7222_parse_all()
2873 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]); in iqs7222_parse_all()
2876 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { in iqs7222_parse_all()
2879 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK; in iqs7222_parse_all()
2880 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN; in iqs7222_parse_all()
2882 chan_setup[5] = 0; in iqs7222_parse_all()
2885 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { in iqs7222_parse_all()
2888 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK; in iqs7222_parse_all()
2891 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { in iqs7222_parse_all()
2892 for (j = 0; j < reg_grps[i].num_row; j++) { in iqs7222_parse_all()
2899 return 0; in iqs7222_parse_all()
2916 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) { in iqs7222_report()
2921 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) { in iqs7222_report()
2926 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE) in iqs7222_report()
2927 return 0; in iqs7222_report()
2929 for (i = 0; i < num_chan; i++) { in iqs7222_report()
2932 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN)) in iqs7222_report()
2935 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) { in iqs7222_report()
2956 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { in iqs7222_report()
2961 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK)) in iqs7222_report()
2968 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0], in iqs7222_report()
2998 iqs7222->sl_code[i][j], 0); in iqs7222_report()
3001 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) { in iqs7222_report()
3006 input_report_key(iqs7222->keypad, iqs7222->tp_code[0], in iqs7222_report()
3033 iqs7222->tp_code[j], 0); in iqs7222_report()
3038 return 0; in iqs7222_report()
3121 if (irq < 0) in iqs7222_probe()