Lines Matching +full:0 +full:x7220
66 #define QIB_CHIP_VERS_MIN 0U
69 #define QIB_OUI 0x001175
259 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
260 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
261 #define QIB_SDMA_TXREQ_F_INTREQ 0x4
262 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8
263 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10
265 #define QIB_SDMA_TXREQ_S_OK 0
275 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
302 #define IB_LINKCMD_DOWN (0 << 16)
305 #define IB_LINKINITCMD_NOP 0
313 #define QIB_IB_LINKDOWN 0
347 #define QIB_RCVCTRL_TAILUPD_ENB 0x01
348 #define QIB_RCVCTRL_TAILUPD_DIS 0x02
349 #define QIB_RCVCTRL_CTXT_ENB 0x04
350 #define QIB_RCVCTRL_CTXT_DIS 0x08
351 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
352 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
353 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
354 #define QIB_RCVCTRL_PKEY_DIS 0x80
355 #define QIB_RCVCTRL_BP_ENB 0x0100
356 #define QIB_RCVCTRL_BP_DIS 0x0200
357 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
358 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
367 #define QIB_SENDCTRL_DISARM (0x1000)
369 /* available (0x2000) */
370 #define QIB_SENDCTRL_AVAIL_DIS (0x4000)
371 #define QIB_SENDCTRL_AVAIL_ENB (0x8000)
372 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
373 #define QIB_SENDCTRL_SEND_DIS (0x20000)
374 #define QIB_SENDCTRL_SEND_ENB (0x40000)
375 #define QIB_SENDCTRL_FLUSH (0x80000)
376 #define QIB_SENDCTRL_CLEAR (0x100000)
377 #define QIB_SENDCTRL_DISARM_ALL (0x200000)
386 #define QIBPORTCNTR_PKTSEND 0U
613 /* list of pkeys programmed; 0 if not set */
729 * data structs, indexed by pidx (0..n-1)
1078 #define QIB_HOL_UP 0
1081 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1091 #define TXCHK_CHG_TYPE_USER 0
1202 u32 pidx = port - 1; /* IB number port from 1, hdw from 0 */ in to_iport()
1211 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */
1212 #define QIB_INITTED 0x2 /* chip and driver up and initted */
1213 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */
1214 #define QIB_PRESENT 0x8 /* chip accesses can be done */
1215 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */
1216 #define QIB_HAS_THRESH_UPDATE 0x40
1217 #define QIB_HAS_SDMA_TIMEOUT 0x80
1218 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */
1219 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */
1220 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */
1221 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */
1222 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */
1223 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */
1224 #define QIB_BADINTR 0x8000 /* severe interrupt problems */
1225 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */
1226 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */
1227 #define QIB_SHUTDOWN 0x40000 /* device is shutting down */
1232 #define QIBL_LINKV 0x1 /* IB link state valid */
1233 #define QIBL_LINKDOWN 0x8 /* IB link is down */
1234 #define QIBL_LINKINIT 0x10 /* IB link level is up */
1235 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */
1236 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */
1238 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */
1239 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */
1240 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced,
1242 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */
1269 #define QIB_TWSI_NO_DEV 0xFF
1345 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL; in qib_clear_rcvhdrtail()
1392 * dma_addr wrappers - all 0's invalid for hw
1414 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
1427 #define QIB_USER_MINOR_BASE 0
1433 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1434 #define PCI_VENDOR_ID_QLOGIC 0x1077
1435 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1436 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1437 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322