1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/iio/timer/stm32-timer-trigger.h>
13 #include <linux/mfd/stm32-timers.h>
129 	div = (unsigned long long)clk_get_rate(priv->clk);  in stm32_timer_start()
139 	while (div > priv->max_arr) {  in stm32_timer_start()
147 		dev_err(priv->dev, "prescaler exceeds the maximum value\n");  in stm32_timer_start()
148 		return -EINVAL;  in stm32_timer_start()
152 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_timer_start()
154 		return -EBUSY;  in stm32_timer_start()
156 	guard(mutex)(&priv->lock);  in stm32_timer_start()
157 	if (!priv->enabled) {  in stm32_timer_start()
158 		priv->enabled = true;  in stm32_timer_start()
159 		ret = clk_enable(priv->clk);  in stm32_timer_start()
164 	regmap_write(priv->regmap, TIM_PSC, prescaler);  in stm32_timer_start()
165 	regmap_write(priv->regmap, TIM_ARR, prd - 1);  in stm32_timer_start()
166 	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);  in stm32_timer_start()
169 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_timer_start()
170 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,  in stm32_timer_start()
173 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,  in stm32_timer_start()
177 	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);  in stm32_timer_start()
180 	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);  in stm32_timer_start()
190 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_timer_stop()
194 	mutex_lock(&priv->lock);  in stm32_timer_stop()
196 	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);  in stm32_timer_stop()
197 	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);  in stm32_timer_stop()
198 	regmap_write(priv->regmap, TIM_PSC, 0);  in stm32_timer_stop()
199 	regmap_write(priv->regmap, TIM_ARR, 0);  in stm32_timer_stop()
202 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_timer_stop()
203 		regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);  in stm32_timer_stop()
205 		regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS);  in stm32_timer_stop()
208 	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);  in stm32_timer_stop()
210 	if (priv->enabled) {  in stm32_timer_stop()
211 		priv->enabled = false;  in stm32_timer_stop()
212 		clk_disable(priv->clk);  in stm32_timer_stop()
214 	mutex_unlock(&priv->lock);  in stm32_timer_stop()
249 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_tt_read_frequency()
250 	regmap_read(priv->regmap, TIM_PSC, &psc);  in stm32_tt_read_frequency()
251 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_tt_read_frequency()
254 		freq = (unsigned long long)clk_get_rate(priv->clk);  in stm32_tt_read_frequency()
297 	regmap_read(priv->regmap, TIM_CR2, &cr2);  in stm32_tt_show_master_mode()
299 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_tt_show_master_mode()
316 	if (stm32_timer_is_trgo2_name(trig->name)) {  in stm32_tt_store_master_mode()
329 			guard(mutex)(&priv->lock);  in stm32_tt_store_master_mode()
330 			if (!priv->enabled) {  in stm32_tt_store_master_mode()
332 				priv->enabled = true;  in stm32_tt_store_master_mode()
333 				ret = clk_enable(priv->clk);  in stm32_tt_store_master_mode()
337 			regmap_update_bits(priv->regmap, TIM_CR2, mask,  in stm32_tt_store_master_mode()
343 	return -EINVAL;  in stm32_tt_store_master_mode()
354 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_tt_show_master_mode_avail()
360 		len += scnprintf(buf + len, PAGE_SIZE - len,  in stm32_tt_show_master_mode_avail()
364 	buf[len - 1] = '\n';  in stm32_tt_show_master_mode_avail()
400 	list_for_each_entry(tr, &priv->tr_list, alloc_list)  in stm32_unregister_iio_triggers()
407 	const char * const *cur = priv->triggers;  in stm32_register_iio_triggers()
409 	INIT_LIST_HEAD(&priv->tr_list);  in stm32_register_iio_triggers()
416 		if (cur_is_trgo2 && !priv->has_trgo2) {  in stm32_register_iio_triggers()
421 		trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);  in stm32_register_iio_triggers()
423 			return -ENOMEM;  in stm32_register_iio_triggers()
425 		trig->dev.parent = priv->dev->parent;  in stm32_register_iio_triggers()
426 		trig->ops = &timer_trigger_ops;  in stm32_register_iio_triggers()
433 			trig->dev.groups = stm32_trigger_attr_groups;  in stm32_register_iio_triggers()
443 		list_add_tail(&trig->alloc_list, &priv->tr_list);  in stm32_register_iio_triggers()
459 		regmap_read(priv->regmap, TIM_CNT, &dat);  in stm32_counter_read_raw()
464 		regmap_read(priv->regmap, TIM_CR1, &dat);  in stm32_counter_read_raw()
469 		regmap_read(priv->regmap, TIM_SMCR, &dat);  in stm32_counter_read_raw()
482 	return -EINVAL;  in stm32_counter_read_raw()
494 		return regmap_write(priv->regmap, TIM_CNT, val);  in stm32_counter_write_raw()
498 		return -EINVAL;  in stm32_counter_write_raw()
501 		guard(mutex)(&priv->lock);  in stm32_counter_write_raw()
503 			if (!priv->enabled) {  in stm32_counter_write_raw()
504 				priv->enabled = true;  in stm32_counter_write_raw()
505 				ret = clk_enable(priv->clk);  in stm32_counter_write_raw()
509 			regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);  in stm32_counter_write_raw()
511 			regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);  in stm32_counter_write_raw()
512 			if (priv->enabled) {  in stm32_counter_write_raw()
513 				priv->enabled = false;  in stm32_counter_write_raw()
514 				clk_disable(priv->clk);  in stm32_counter_write_raw()
521 		return -EINVAL;  in stm32_counter_write_raw()
529 	const char * const *cur = priv->valids;  in stm32_counter_validate_trigger()
533 		return -EINVAL;  in stm32_counter_validate_trigger()
536 		if (!strncmp(trig->name, *cur, strlen(trig->name))) {  in stm32_counter_validate_trigger()
537 			regmap_update_bits(priv->regmap,  in stm32_counter_validate_trigger()
546 	return -EINVAL;  in stm32_counter_validate_trigger()
565 	regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS);  in stm32_set_trigger_mode()
576 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_get_trigger_mode()
578 	return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;  in stm32_get_trigger_mode()
605 	return -EINVAL;  in stm32_enable_mode2sms()
622 	scoped_guard(mutex, &priv->lock) {  in stm32_set_enable_mode()
623 		if (sms == 6 && !priv->enabled) {  in stm32_set_enable_mode()
624 			ret = clk_enable(priv->clk);  in stm32_set_enable_mode()
628 			priv->enabled = true;  in stm32_set_enable_mode()
632 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);  in stm32_set_enable_mode()
648 	return -EINVAL;  in stm32_sms2enable_mode()
657 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_get_enable_mode()
678 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_count_get_preset()
697 	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);  in stm32_count_set_preset()
698 	regmap_write(priv->regmap, TIM_ARR, preset);  in stm32_count_set_preset()
737 	indio_dev->name = dev_name(dev);  in stm32_setup_counter_device()
738 	indio_dev->info = &stm32_trigger_info;  in stm32_setup_counter_device()
739 	indio_dev->modes = INDIO_HARDWARE_TRIGGERED;  in stm32_setup_counter_device()
740 	indio_dev->num_channels = 1;  in stm32_setup_counter_device()
741 	indio_dev->channels = &stm32_trigger_channel;  in stm32_setup_counter_device()
754  * return true if the trigger is a valid stm32 iio timer trigger
759 	return (trig->ops == &timer_trigger_ops);  in is_stm32_timer_trigger()
771 	regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);  in stm32_timer_detect_trgo2()
772 	regmap_read(priv->regmap, TIM_CR2, &val);  in stm32_timer_detect_trgo2()
773 	regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);  in stm32_timer_detect_trgo2()
774 	priv->has_trgo2 = !!val;  in stm32_timer_detect_trgo2()
779 	struct device *dev = &pdev->dev;  in stm32_timer_trigger_probe()
781 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);  in stm32_timer_trigger_probe()
793 	    index >= cfg->num_valids_table)  in stm32_timer_trigger_probe()
794 		return -EINVAL;  in stm32_timer_trigger_probe()
797 	if (cfg->valids_table && *cfg->valids_table[index])  in stm32_timer_trigger_probe()
803 		return -ENOMEM;  in stm32_timer_trigger_probe()
805 	priv->dev = dev;  in stm32_timer_trigger_probe()
806 	priv->regmap = ddata->regmap;  in stm32_timer_trigger_probe()
807 	priv->clk = ddata->clk;  in stm32_timer_trigger_probe()
808 	priv->max_arr = ddata->max_arr;  in stm32_timer_trigger_probe()
809 	priv->triggers = triggers_table[index];  in stm32_timer_trigger_probe()
810 	if (cfg->valids_table && *cfg->valids_table[index])  in stm32_timer_trigger_probe()
811 		priv->valids = cfg->valids_table[index];  in stm32_timer_trigger_probe()
813 	mutex_init(&priv->lock);  in stm32_timer_trigger_probe()
833 	regmap_read(priv->regmap, TIM_CCER, &val);  in stm32_timer_trigger_remove()
835 		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);  in stm32_timer_trigger_remove()
837 	if (priv->enabled)  in stm32_timer_trigger_remove()
838 		clk_disable(priv->clk);  in stm32_timer_trigger_remove()
846 	if (priv->enabled) {  in stm32_timer_trigger_suspend()
848 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);  in stm32_timer_trigger_suspend()
849 		regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);  in stm32_timer_trigger_suspend()
850 		regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);  in stm32_timer_trigger_suspend()
851 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);  in stm32_timer_trigger_suspend()
852 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);  in stm32_timer_trigger_suspend()
853 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);  in stm32_timer_trigger_suspend()
856 		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);  in stm32_timer_trigger_suspend()
857 		clk_disable(priv->clk);  in stm32_timer_trigger_suspend()
868 	if (priv->enabled) {  in stm32_timer_trigger_resume()
869 		ret = clk_enable(priv->clk);  in stm32_timer_trigger_resume()
874 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);  in stm32_timer_trigger_resume()
875 		regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);  in stm32_timer_trigger_resume()
878 		regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);  in stm32_timer_trigger_resume()
879 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);  in stm32_timer_trigger_resume()
880 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);  in stm32_timer_trigger_resume()
882 		/* Also re-enables the timer */  in stm32_timer_trigger_resume()
883 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);  in stm32_timer_trigger_resume()
908 	 * point to the stm32-timer-cnt driver instead.
915 		.compatible = "st,stm32-timer-trigger",
918 		.compatible = "st,stm32h7-timer-trigger",
921 		.compatible = "st,stm32mp25-timer-trigger",
932 		.name = "stm32-timer-trigger",
939 MODULE_ALIAS("platform:stm32-timer-trigger");
940 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");