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1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AD3552R Digital <-> Analog converters common header
5 * Copyright 2021-2024 Analog Devices Inc.
15 #define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))
16 #define AD3552R_MASK_ADDR_ASCENSION BIT(5)
17 #define AD3552R_MASK_SDO_ACTIVE BIT(4)
19 #define AD3552R_MASK_SINGLE_INST BIT(7)
20 #define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
22 #define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))
40 #define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE BIT(2)
44 #define AD3552R_MASK_STRICT_REGISTER_ACCESS BIT(5)
46 #define AD3552R_MASK_INTERFACE_NOT_READY BIT(7)
47 #define AD3552R_MASK_CLOCK_COUNTING_ERROR BIT(5)
48 #define AD3552R_MASK_INVALID_OR_NO_CRC BIT(3)
49 #define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER BIT(2)
50 #define AD3552R_MASK_PARTIAL_REGISTER_ACCESS BIT(1)
51 #define AD3552R_MASK_REGISTER_ADDRESS_INVALID BIT(0)
53 #define AD3552R_MASK_ALERT_ENABLE_PULLUP BIT(6)
54 #define AD3552R_MASK_MEM_CRC_EN BIT(4)
56 #define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN BIT(1)
57 #define AD3552R_MASK_SPI_CONFIG_DDR BIT(0)
59 #define AD3552R_MASK_IDUMP_FAST_MODE BIT(6)
60 #define AD3552R_MASK_SAMPLE_HOLD_DIFF_USER_EN BIT(5)
62 #define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE BIT(2)
65 #define AD3552R_MASK_REF_RANGE_ALARM BIT(6)
66 #define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM BIT(5)
67 #define AD3552R_MASK_MEM_CRC_ERR_ALARM BIT(4)
68 #define AD3552R_MASK_SPI_CRC_ERR_ALARM BIT(3)
69 #define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM BIT(2)
70 #define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM BIT(1)
71 #define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM BIT(0)
73 #define AD3552R_MASK_REF_RANGE_ERR_STATUS BIT(6)
74 #define AD3552R_MASK_STREAM_EXCEEDS_DAC_ERR_STATUS BIT(5)
75 #define AD3552R_MASK_MEM_CRC_ERR_STATUS BIT(4)
76 #define AD3552R_MASK_RESET_STATUS BIT(0)
78 #define AD3552R_MASK_CH_DAC_POWERDOWN(ch) BIT(4 + (ch))
79 #define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch) BIT(ch)
89 #define AD3552R_MASK_CH_RANGE_OVERRIDE BIT(7)
92 #define AD3552R_MASK_CH_OFFSET_POLARITY BIT(2)
93 #define AD3552R_MASK_CH_OFFSET_BIT_8 BIT(8)
101 #define AD3552R_REG_ADDR_CH_DAC_16B(ch) (0x2C - (1 - (ch)) * 2)
106 #define AD3552R_REG_ADDR_CH_INPUT_16B(ch) (0x36 - (1 - (ch)) * 2)
110 #define AD3552R_REG_ADDR_CH_DAC_24B(ch) (0x3D - (1 - (ch)) * 3)
115 #define AD3552R_REG_ADDR_CH_INPUT_24B(ch) (0x4B - (1 - (ch)) * 3)
118 #define AD3552R_MASK_CH(ch) BIT(ch)
121 #define AD3552R_READ_BIT BIT(7)
130 #define AD3552R_CH0_ACTIVE BIT(0)
131 #define AD3552R_CH1_ACTIVE BIT(1)
183 /* Internal source with Vref I/O at 2.5V */
190 /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
192 /* Range from 0 V to 5 V. Requires Rfb1x connection */
194 /* Range from 0 V to 10 V. Requires Rfb2x connection */
196 /* Range from -5 V to 5 V. Requires Rfb2x connection */
198 /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */
203 /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
205 /* Range from 0 V to 5 V. Requires Rfb1x connection */
207 /* Range from 0 V to 10 V. Requires Rfb2x connection */
209 /* Range from -5 V to 5 V. Requires Rfb2x connection */
211 /* Range from -10 V to 10 V. Requires Rfb4x connection */