32 static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st,  in ad3552r_qspi_update_reg_bits()  argument
39 	ret = st->data->bus_reg_read(st->back, reg, &rval, xfer_size);  in ad3552r_qspi_update_reg_bits()
45 	return st->data->bus_reg_write(st->back, reg, rval, xfer_size);  in ad3552r_qspi_update_reg_bits()
52 	struct ad3552r_hs_state *st = iio_priv(indio_dev);  in ad3552r_hs_read_raw()  local
62 		*val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz *  in ad3552r_hs_read_raw()
68 		ret = st->data->bus_reg_read(st->back,  in ad3552r_hs_read_raw()
76 		*val = st->ch_data[ch].scale_int;  in ad3552r_hs_read_raw()
77 		*val2 = st->ch_data[ch].scale_dec;  in ad3552r_hs_read_raw()
80 		*val = st->ch_data[ch].offset_int;  in ad3552r_hs_read_raw()
81 		*val2 = st->ch_data[ch].offset_dec;  in ad3552r_hs_read_raw()
92 	struct ad3552r_hs_state *st = iio_priv(indio_dev);  in ad3552r_hs_write_raw()  local
97 			return st->data->bus_reg_write(st->back,  in ad3552r_hs_write_raw()
109 	struct ad3552r_hs_state *st = iio_priv(indio_dev);  in ad3552r_hs_buffer_postenable()  local
117 		st->single_channel = true;  in ad3552r_hs_buffer_postenable()
122 		st->single_channel = true;  in ad3552r_hs_buffer_postenable()
127 		st->single_channel = false;  in ad3552r_hs_buffer_postenable()
135 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_STREAM_MODE,  in ad3552r_hs_buffer_postenable()
141 	ret = ad3552r_qspi_update_reg_bits(st,  in ad3552r_hs_buffer_postenable()
149 	ret = iio_backend_ddr_enable(st->back);  in ad3552r_hs_buffer_postenable()
151 		dev_err(st->dev, "could not set DDR mode, not streaming");  in ad3552r_hs_buffer_postenable()
155 	ret = iio_backend_data_transfer_addr(st->back, val);  in ad3552r_hs_buffer_postenable()
159 	ret = iio_backend_data_format_set(st->back, 0, &fmt);  in ad3552r_hs_buffer_postenable()
163 	ret = iio_backend_data_stream_enable(st->back);  in ad3552r_hs_buffer_postenable()
170 	ad3552r_qspi_update_reg_bits(st,  in ad3552r_hs_buffer_postenable()
175 	iio_backend_ddr_disable(st->back);  in ad3552r_hs_buffer_postenable()
182 	struct ad3552r_hs_state *st = iio_priv(indio_dev);  in ad3552r_hs_buffer_predisable()  local
185 	ret = iio_backend_data_stream_disable(st->back);  in ad3552r_hs_buffer_predisable()
190 	ret = ad3552r_qspi_update_reg_bits(st,  in ad3552r_hs_buffer_predisable()
197 	ret = iio_backend_ddr_disable(st->back);  in ad3552r_hs_buffer_predisable()
204 static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st,  in ad3552r_hs_set_output_range()  argument
214 	return ad3552r_qspi_update_reg_bits(st,  in ad3552r_hs_set_output_range()
220 static int ad3552r_hs_reset(struct ad3552r_hs_state *st)  in ad3552r_hs_reset()  argument
224 	st->reset_gpio = devm_gpiod_get_optional(st->dev,  in ad3552r_hs_reset()
226 	if (IS_ERR(st->reset_gpio))  in ad3552r_hs_reset()
227 		return PTR_ERR(st->reset_gpio);  in ad3552r_hs_reset()
229 	if (st->reset_gpio) {  in ad3552r_hs_reset()
231 		gpiod_set_value_cansleep(st->reset_gpio, 0);  in ad3552r_hs_reset()
233 		ret = ad3552r_qspi_update_reg_bits(st,  in ad3552r_hs_reset()
245 static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st)  in ad3552r_hs_scratch_pad_test()  argument
249 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
254 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
260 		return dev_err_probe(st->dev, -EIO,  in ad3552r_hs_scratch_pad_test()
264 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
269 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
275 		return dev_err_probe(st->dev, -EIO,  in ad3552r_hs_scratch_pad_test()
282 static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st,  in ad3552r_hs_setup_custom_gain()  argument
287 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch),  in ad3552r_hs_setup_custom_gain()
292 	return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch),  in ad3552r_hs_setup_custom_gain()
296 static int ad3552r_hs_setup(struct ad3552r_hs_state *st)  in ad3552r_hs_setup()  argument
303 	ret = ad3552r_hs_reset(st);  in ad3552r_hs_setup()
307 	ret = iio_backend_ddr_disable(st->back);  in ad3552r_hs_setup()
311 	ret = ad3552r_hs_scratch_pad_test(st);  in ad3552r_hs_setup()
315 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_L,  in ad3552r_hs_setup()
322 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_H,  in ad3552r_hs_setup()
328 	if (id != st->model_data->chip_id)  in ad3552r_hs_setup()
329 		dev_info(st->dev, "Chip ID error. Expected 0x%x, Read 0x%x\n",  in ad3552r_hs_setup()
333 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS,  in ad3552r_hs_setup()
338 	ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_setup()
344 	ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_setup()
352 	ret = iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL);  in ad3552r_hs_setup()
356 	ret = iio_backend_data_source_set(st->back, 1, IIO_BACKEND_EXTERNAL);  in ad3552r_hs_setup()
360 	ret = ad3552r_get_ref_voltage(st->dev, &val);  in ad3552r_hs_setup()
366 	ret = ad3552r_qspi_update_reg_bits(st,  in ad3552r_hs_setup()
373 	ret = ad3552r_get_drive_strength(st->dev, &val);  in ad3552r_hs_setup()
375 		ret = ad3552r_qspi_update_reg_bits(st,  in ad3552r_hs_setup()
383 	device_for_each_child_node_scoped(st->dev, child) {  in ad3552r_hs_setup()
386 			return dev_err_probe(st->dev, ret,  in ad3552r_hs_setup()
389 		ret = ad3552r_get_output_range(st->dev, st->model_data, child,  in ad3552r_hs_setup()
394 			ret = ad3552r_get_custom_gain(st->dev, child,  in ad3552r_hs_setup()
395 						&st->ch_data[ch].p,  in ad3552r_hs_setup()
396 						&st->ch_data[ch].n,  in ad3552r_hs_setup()
397 						&st->ch_data[ch].rfb,  in ad3552r_hs_setup()
398 						&st->ch_data[ch].gain_offset);  in ad3552r_hs_setup()
402 			gain = ad3552r_calc_custom_gain(st->ch_data[ch].p,  in ad3552r_hs_setup()
403 						st->ch_data[ch].n,  in ad3552r_hs_setup()
404 						st->ch_data[ch].gain_offset);  in ad3552r_hs_setup()
405 			offset = abs(st->ch_data[ch].gain_offset);  in ad3552r_hs_setup()
407 			st->ch_data[ch].range_override = 1;  in ad3552r_hs_setup()
409 			ret = ad3552r_hs_setup_custom_gain(st, ch, gain,  in ad3552r_hs_setup()
414 			st->ch_data[ch].range = range;  in ad3552r_hs_setup()
416 			ret = ad3552r_hs_set_output_range(st, ch, range);  in ad3552r_hs_setup()
421 		ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data);  in ad3552r_hs_setup()
462 	struct ad3552r_hs_state *st;  in ad3552r_hs_probe()  local
466 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));  in ad3552r_hs_probe()
470 	st = iio_priv(indio_dev);  in ad3552r_hs_probe()
471 	st->dev = &pdev->dev;  in ad3552r_hs_probe()
473 	st->data = dev_get_platdata(st->dev);  in ad3552r_hs_probe()
474 	if (!st->data)  in ad3552r_hs_probe()
475 		return dev_err_probe(st->dev, -ENODEV, "No platform data !");  in ad3552r_hs_probe()
477 	st->back = devm_iio_backend_get(&pdev->dev, NULL);  in ad3552r_hs_probe()
478 	if (IS_ERR(st->back))  in ad3552r_hs_probe()
479 		return PTR_ERR(st->back);  in ad3552r_hs_probe()
481 	ret = devm_iio_backend_enable(&pdev->dev, st->back);  in ad3552r_hs_probe()
485 	st->model_data = device_get_match_data(&pdev->dev);  in ad3552r_hs_probe()
486 	if (!st->model_data)  in ad3552r_hs_probe()
496 	ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev);  in ad3552r_hs_probe()
500 	ret = ad3552r_hs_setup(st);  in ad3552r_hs_probe()