1 // SPDX-License-Identifier: GPL-2.0
7  * Author: Lad Prabhakar <prabhakar.mahadev-[email protected]>
25 #define DRIVER_NAME		"rzg2l-adc"
27 #define RZG2L_ADM(n)			((n) * 0x4)  argument
52 #define RZG2L_ADCR(n)			(0x30 + ((n) * 0x4))  argument
59  * struct rzg2l_adc_hw_params - ADC hardware specific parameters
95  * struct rzg2l_adc_channel - ADC channel descriptor
118 	return readl(adc->base + reg);  in rzg2l_adc_readl()
123 	writel(val, adc->base + reg);  in rzg2l_adc_writel()
157 		pr_err("%s stopping ADC timed out\n", __func__);  in rzg2l_adc_start_stop()
166 	 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid  in rzg2l_set_trigger()
167 	 * BS[4] - Enable 1-buffer mode  in rzg2l_set_trigger()
168 	 * MS[1] - Enable Select mode  in rzg2l_set_trigger()
169 	 * TRG[0] - Enable software trigger mode  in rzg2l_set_trigger()
189 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;  in rzg2l_adc_conversion_setup()
194 		return -EBUSY;  in rzg2l_adc_conversion_setup()
200 	reg &= ~GENMASK(hw_params->num_channels - 1, 0);  in rzg2l_adc_conversion_setup()
205 	reg &= ~hw_params->adsmp_mask;  in rzg2l_adc_conversion_setup()
206 	reg |= hw_params->default_adsmp[index];  in rzg2l_adc_conversion_setup()
211 	 * INTS[31] - Select pulse signal  in rzg2l_adc_conversion_setup()
212 	 * CSEEN[16] - Enable channel select error interrupt  in rzg2l_adc_conversion_setup()
213 	 * INTEN[7:0] - Select channel interrupt  in rzg2l_adc_conversion_setup()
217 	reg &= ~hw_params->adint_inten_mask;  in rzg2l_adc_conversion_setup()
226 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;  in rzg2l_adc_conversion()
227 	struct device *dev = indio_dev->dev.parent;  in rzg2l_adc_conversion()
238 	reinit_completion(&adc->completion);  in rzg2l_adc_conversion()
242 	if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {  in rzg2l_adc_conversion()
244 				 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);  in rzg2l_adc_conversion()
245 		ret = -ETIMEDOUT;  in rzg2l_adc_conversion()
265 		if (chan->type != IIO_VOLTAGE && chan->type != IIO_TEMP)  in rzg2l_adc_read_raw()
266 			return -EINVAL;  in rzg2l_adc_read_raw()
268 		guard(mutex)(&adc->lock);  in rzg2l_adc_read_raw()
270 		ret = rzg2l_adc_conversion(indio_dev, adc, chan->channel);  in rzg2l_adc_read_raw()
274 		*val = adc->last_val[chan->channel];  in rzg2l_adc_read_raw()
280 		return -EINVAL;  in rzg2l_adc_read_raw()
288 	return sysfs_emit(label, "%s\n", rzg2l_adc_channels[chan->channel].name);  in rzg2l_adc_read_label()
299 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;  in rzg2l_adc_isr()
312 	intst = reg & GENMASK(hw_params->num_channels - 1, 0);  in rzg2l_adc_isr()
316 	for_each_set_bit(ch, &intst, hw_params->num_channels)  in rzg2l_adc_isr()
317 		adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;  in rzg2l_adc_isr()
322 	complete(&adc->completion);  in rzg2l_adc_isr()
329 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;  in rzg2l_adc_parse_properties()
337 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);  in rzg2l_adc_parse_properties()
339 		return -ENOMEM;  in rzg2l_adc_parse_properties()
341 	num_channels = device_get_child_node_count(&pdev->dev);  in rzg2l_adc_parse_properties()
343 		return dev_err_probe(&pdev->dev, -ENODEV, "no channel children\n");  in rzg2l_adc_parse_properties()
345 	if (num_channels > hw_params->num_channels)  in rzg2l_adc_parse_properties()
346 		return dev_err_probe(&pdev->dev, -EINVAL,  in rzg2l_adc_parse_properties()
347 				     "num of channel children out of range\n");  in rzg2l_adc_parse_properties()
349 	chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),  in rzg2l_adc_parse_properties()
352 		return -ENOMEM;  in rzg2l_adc_parse_properties()
355 	device_for_each_child_node_scoped(&pdev->dev, fwnode) {  in rzg2l_adc_parse_properties()
360 		if (channel >= hw_params->num_channels)  in rzg2l_adc_parse_properties()
361 			return -EINVAL;  in rzg2l_adc_parse_properties()
371 	data->num_channels = num_channels;  in rzg2l_adc_parse_properties()
372 	data->channels = chan_array;  in rzg2l_adc_parse_properties()
373 	adc->data = data;  in rzg2l_adc_parse_properties()
380 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;  in rzg2l_adc_hw_init()
398 	if (hw_params->adivc) {  in rzg2l_adc_hw_init()
408 	 * ADIL[31:24] - Should be always set to 0  in rzg2l_adc_hw_init()
409 	 * ADCMP[23:16] - Should be always set to 0xe  in rzg2l_adc_hw_init()
410 	 * ADSMP[15:0] - Set default (0x578) sampling period  in rzg2l_adc_hw_init()
415 	reg &= ~hw_params->adsmp_mask;  in rzg2l_adc_hw_init()
416 	reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) |  in rzg2l_adc_hw_init()
417 	       hw_params->default_adsmp[0];  in rzg2l_adc_hw_init()
429 	struct device *dev = &pdev->dev;  in rzg2l_adc_probe()
437 		return -ENOMEM;  in rzg2l_adc_probe()
441 	adc->hw_params = device_get_match_data(dev);  in rzg2l_adc_probe()
442 	if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS)  in rzg2l_adc_probe()
443 		return -EINVAL;  in rzg2l_adc_probe()
449 	mutex_init(&adc->lock);  in rzg2l_adc_probe()
451 	adc->base = devm_platform_ioremap_resource(pdev, 0);  in rzg2l_adc_probe()
452 	if (IS_ERR(adc->base))  in rzg2l_adc_probe()
453 		return PTR_ERR(adc->base);  in rzg2l_adc_probe()
455 	adc->adrstn = devm_reset_control_get_exclusive_deasserted(dev, "adrst-n");  in rzg2l_adc_probe()
456 	if (IS_ERR(adc->adrstn))  in rzg2l_adc_probe()
457 		return dev_err_probe(dev, PTR_ERR(adc->adrstn),  in rzg2l_adc_probe()
458 				     "failed to get/deassert adrst-n\n");  in rzg2l_adc_probe()
460 	adc->presetn = devm_reset_control_get_exclusive_deasserted(dev, "presetn");  in rzg2l_adc_probe()
461 	if (IS_ERR(adc->presetn))  in rzg2l_adc_probe()
462 		return dev_err_probe(dev, PTR_ERR(adc->presetn),  in rzg2l_adc_probe()
463 				     "failed to get/deassert presetn\n");  in rzg2l_adc_probe()
475 		return dev_err_probe(&pdev->dev, ret,  in rzg2l_adc_probe()
476 				     "failed to initialize ADC HW\n");  in rzg2l_adc_probe()
487 	init_completion(&adc->completion);  in rzg2l_adc_probe()
489 	indio_dev->name = DRIVER_NAME;  in rzg2l_adc_probe()
490 	indio_dev->info = &rzg2l_adc_iio_info;  in rzg2l_adc_probe()
491 	indio_dev->modes = INDIO_DIRECT_MODE;  in rzg2l_adc_probe()
492 	indio_dev->channels = adc->data->channels;  in rzg2l_adc_probe()
493 	indio_dev->num_channels = adc->data->num_channels;  in rzg2l_adc_probe()
516 	{ .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
517 	{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
547 		{ .rstc = adc->presetn },  in rzg2l_adc_suspend()
548 		{ .rstc = adc->adrstn },  in rzg2l_adc_suspend()
553 		adc->was_rpm_active = false;  in rzg2l_adc_suspend()
558 		adc->was_rpm_active = true;  in rzg2l_adc_suspend()
568 	if (adc->was_rpm_active)  in rzg2l_adc_suspend()
579 		{ .rstc = adc->adrstn },  in rzg2l_adc_resume()
580 		{ .rstc = adc->presetn },  in rzg2l_adc_resume()
588 	if (adc->was_rpm_active) {  in rzg2l_adc_resume()
601 	if (adc->was_rpm_active) {  in rzg2l_adc_resume()
626 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-[email protected]>");