1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright 2011-2015 Analog Devices Inc.
11 #include <linux/clk-provider.h>
35 #define AD7192_REG_COMM		0 /* Communications Register (WO, 8-bit) */
36 #define AD7192_REG_STAT		0 /* Status Register	     (RO, 8-bit) */
37 #define AD7192_REG_MODE		1 /* Mode Register	     (RW, 24-bit */
38 #define AD7192_REG_CONF		2 /* Configuration Register  (RW, 24-bit) */
39 #define AD7192_REG_DATA		3 /* Data Register	     (RO, 24/32-bit) */
40 #define AD7192_REG_ID		4 /* ID Register	     (RO, 8-bit) */
41 #define AD7192_REG_GPOCON	5 /* GPOCON Register	     (RO, 8-bit) */
42 #define AD7192_REG_OFFSET	6 /* Offset Register	     (RW, 16-bit */
43 				  /* (AD7792)/24-bit (AD7192)) */
44 #define AD7192_REG_FULLSALE	7 /* Full-Scale Register */
45 				  /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
81 #define AD7192_MODE_PWRDN		3 /* Power-Down Mode */
82 #define AD7192_MODE_CAL_INT_ZERO	4 /* Internal Zero-Scale Calibration */
83 #define AD7192_MODE_CAL_INT_FULL	5 /* Internal Full-Scale Calibration */
84 #define AD7192_MODE_CAL_SYS_ZERO	6 /* System Zero-Scale Calibration */
85 #define AD7192_MODE_CAL_SYS_FULL	7 /* System Full-Scale Calibration */
108 #define AD7192_CH_AIN1P_AIN2M	BIT(0) /* AIN1(+) - AIN2(-) */
109 #define AD7192_CH_AIN3P_AIN4M	BIT(1) /* AIN3(+) - AIN4(-) */
111 #define AD7192_CH_AIN2P_AIN2M	BIT(3) /* AIN2(+) - AIN2(-) */
112 #define AD7192_CH_AIN1		BIT(4) /* AIN1 - AINCOM */
113 #define AD7192_CH_AIN2		BIT(5) /* AIN2 - AINCOM */
114 #define AD7192_CH_AIN3		BIT(6) /* AIN3 - AINCOM */
115 #define AD7192_CH_AIN4		BIT(7) /* AIN4 - AINCOM */
117 #define AD7193_CH_AIN1P_AIN2M	0x001  /* AIN1(+) - AIN2(-) */
118 #define AD7193_CH_AIN3P_AIN4M	0x002  /* AIN3(+) - AIN4(-) */
119 #define AD7193_CH_AIN5P_AIN6M	0x004  /* AIN5(+) - AIN6(-) */
120 #define AD7193_CH_AIN7P_AIN8M	0x008  /* AIN7(+) - AIN8(-) */
122 #define AD7193_CH_AIN2P_AIN2M	0x200 /* AIN2(+) - AIN2(-) */
123 #define AD7193_CH_AIN1		0x401 /* AIN1 - AINCOM */
124 #define AD7193_CH_AIN2		0x402 /* AIN2 - AINCOM */
125 #define AD7193_CH_AIN3		0x404 /* AIN3 - AINCOM */
126 #define AD7193_CH_AIN4		0x408 /* AIN4 - AINCOM */
127 #define AD7193_CH_AIN5		0x410 /* AIN5 - AINCOM */
128 #define AD7193_CH_AIN6		0x420 /* AIN6 - AINCOM */
129 #define AD7193_CH_AIN7		0x440 /* AIN7 - AINCOM */
130 #define AD7193_CH_AIN8		0x480 /* AIN7 - AINCOM */
131 #define AD7193_CH_AINCOM	0x600 /* AINCOM - AINCOM */
133 #define AD7194_CH_POS(x)	(((x) - 1) << 4)
134 #define AD7194_CH_NEG(x)	((x) - 1)
136 /* 10th bit corresponds to CON18(Pseudo) */
155 #define AD7192_GPOCON_BPDSW	BIT(6) /* Bridge power-down switch enable */
233 	st->syscalib_mode[chan->channel] = mode;  in ad7192_set_syscalib_mode()
243 	return st->syscalib_mode[chan->channel];  in ad7192_get_syscalib_mode()
260 		return -EBUSY;  in ad7192_write_syscalib()
262 	temp = st->syscalib_mode[chan->channel];  in ad7192_write_syscalib()
265 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,  in ad7192_write_syscalib()
266 					      chan->address);  in ad7192_write_syscalib()
268 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,  in ad7192_write_syscalib()
269 					      chan->address);  in ad7192_write_syscalib()
306 	st->conf &= ~AD7192_CONF_CHAN_MASK;  in ad7192_set_channel()
307 	st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);  in ad7192_set_channel()
309 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_channel()
317 	st->mode &= ~AD7192_MODE_SEL_MASK;  in ad7192_set_mode()
318 	st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);  in ad7192_set_mode()
320 	return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_mode()
326 	unsigned int mode = st->mode;  in ad7192_append_status()
332 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);  in ad7192_append_status()
336 	st->mode = mode;  in ad7192_append_status()
344 	u32 conf = st->conf;  in ad7192_disable_all()
349 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);  in ad7192_disable_all()
353 	st->conf = conf;  in ad7192_disable_all()
398 	return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,  in ad7192_calibrate_all()
433 	return st->clock_sel == AD7192_CLK_INT_CO;  in ad7192_clk_output_is_enabled()
441 	st->mode &= ~AD7192_MODE_CLKSRC_MASK;  in ad7192_clk_prepare()
442 	st->mode |= AD7192_CLK_INT_CO;  in ad7192_clk_prepare()
444 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_clk_prepare()
448 	st->clock_sel = AD7192_CLK_INT_CO;  in ad7192_clk_prepare()
458 	st->mode &= ~AD7192_MODE_CLKSRC_MASK;  in ad7192_clk_unprepare()
459 	st->mode |= AD7192_CLK_INT;  in ad7192_clk_unprepare()
461 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_clk_unprepare()
465 	st->clock_sel = AD7192_CLK_INT;  in ad7192_clk_unprepare()
477 	struct device *dev = &st->sd.spi->dev;  in ad7192_register_clk_provider()
484 	if (!device_property_present(dev, "#clock-cells"))  in ad7192_register_clk_provider()
487 	init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk",  in ad7192_register_clk_provider()
490 		return -ENOMEM;  in ad7192_register_clk_provider()
494 	st->int_clk_hw.init = &init;  in ad7192_register_clk_provider()
495 	ret = devm_clk_hw_register(dev, &st->int_clk_hw);  in ad7192_register_clk_provider()
500 					   &st->int_clk_hw);  in ad7192_register_clk_provider()
505 	struct device *dev = &st->sd.spi->dev;  in ad7192_clock_setup()
514 	if (device_property_read_bool(dev, "adi,int-clock-output-enable")) {  in ad7192_clock_setup()
515 		st->clock_sel = AD7192_CLK_INT_CO;  in ad7192_clock_setup()
516 		st->fclk = AD7192_INT_FREQ_MHZ;  in ad7192_clock_setup()
517 		dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n");  in ad7192_clock_setup()
521 	if (device_property_read_bool(dev, "adi,clock-xtal")) {  in ad7192_clock_setup()
522 		st->clock_sel = AD7192_CLK_EXT_MCLK1_2;  in ad7192_clock_setup()
523 		st->mclk = devm_clk_get_enabled(dev, "mclk");  in ad7192_clock_setup()
524 		if (IS_ERR(st->mclk))  in ad7192_clock_setup()
525 			return dev_err_probe(dev, PTR_ERR(st->mclk),  in ad7192_clock_setup()
528 		st->fclk = clk_get_rate(st->mclk);  in ad7192_clock_setup()
529 		if (!ad7192_valid_external_frequency(st->fclk))  in ad7192_clock_setup()
530 			return dev_err_probe(dev, -EINVAL,  in ad7192_clock_setup()
533 		dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n");  in ad7192_clock_setup()
537 	ret = device_property_match_property_string(dev, "clock-names",  in ad7192_clock_setup()
541 		st->clock_sel = AD7192_CLK_INT;  in ad7192_clock_setup()
542 		st->fclk = AD7192_INT_FREQ_MHZ;  in ad7192_clock_setup()
551 	st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret;  in ad7192_clock_setup()
553 	st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]);  in ad7192_clock_setup()
554 	if (IS_ERR(st->mclk))  in ad7192_clock_setup()
555 		return dev_err_probe(dev, PTR_ERR(st->mclk),  in ad7192_clock_setup()
558 	st->fclk = clk_get_rate(st->mclk);  in ad7192_clock_setup()
559 	if (!ad7192_valid_external_frequency(st->fclk))  in ad7192_clock_setup()
560 		return dev_err_probe(dev, -EINVAL,  in ad7192_clock_setup()
575 	ret = ad_sd_reset(&st->sd);  in ad7192_setup()
581 	ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);  in ad7192_setup()
587 	if (id != st->chip_info->chip_id)  in ad7192_setup()
589 			 id, st->chip_info->chip_id);  in ad7192_setup()
591 	st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |  in ad7192_setup()
592 		FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |  in ad7192_setup()
595 	st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);  in ad7192_setup()
597 	rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable");  in ad7192_setup()
599 		st->mode |= AD7192_MODE_REJ60;  in ad7192_setup()
601 	refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable");  in ad7192_setup()
602 	if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)  in ad7192_setup()
603 		st->conf |= AD7192_CONF_REFSEL;  in ad7192_setup()
605 	st->conf &= ~AD7192_CONF_CHOP;  in ad7192_setup()
607 	buf_en = device_property_read_bool(dev, "adi,buffer-enable");  in ad7192_setup()
609 		st->conf |= AD7192_CONF_BUF;  in ad7192_setup()
613 		st->conf |= AD7192_CONF_UNIPOLAR;  in ad7192_setup()
616 						    "adi,burnout-currents-enable");  in ad7192_setup()
618 		st->conf |= AD7192_CONF_BURN;  in ad7192_setup()
624 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_setup()
628 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_setup()
637 	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {  in ad7192_setup()
638 		scale_uv = ((u64)st->int_vref_mv * 100000000)  in ad7192_setup()
639 			>> (indio_dev->channels[0].scan_type.realbits -  in ad7192_setup()
640 			!FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));  in ad7192_setup()
643 		st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;  in ad7192_setup()
644 		st->scale_avail[i][0] = scale_uv;  in ad7192_setup()
647 	st->oversampling_ratio_avail[0] = 1;  in ad7192_setup()
648 	st->oversampling_ratio_avail[1] = 2;  in ad7192_setup()
649 	st->oversampling_ratio_avail[2] = 8;  in ad7192_setup()
650 	st->oversampling_ratio_avail[3] = 16;  in ad7192_setup()
652 	st->filter_freq_avail[0][0] = 600;  in ad7192_setup()
653 	st->filter_freq_avail[1][0] = 800;  in ad7192_setup()
654 	st->filter_freq_avail[2][0] = 2300;  in ad7192_setup()
655 	st->filter_freq_avail[3][0] = 2720;  in ad7192_setup()
657 	st->filter_freq_avail[0][1] = 1000;  in ad7192_setup()
658 	st->filter_freq_avail[1][1] = 1000;  in ad7192_setup()
659 	st->filter_freq_avail[2][1] = 1000;  in ad7192_setup()
660 	st->filter_freq_avail[3][1] = 1000;  in ad7192_setup()
672 	return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));  in ad7192_show_ac_excitation()
683 			  FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));  in ad7192_show_bridge_switch()
705 	switch ((u32)this_attr->address) {  in ad7192_set()
708 			st->gpocon |= AD7192_GPOCON_BPDSW;  in ad7192_set()
710 			st->gpocon &= ~AD7192_GPOCON_BPDSW;  in ad7192_set()
712 		ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);  in ad7192_set()
716 			st->conf |= AD7192_CONF_ACX;  in ad7192_set()
718 			st->conf &= ~AD7192_CONF_ACX;  in ad7192_set()
720 		ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set()
723 		ret = -EINVAL;  in ad7192_set()
735 	avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);  in ad7192_compute_f_order()
740 	oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];  in ad7192_compute_f_order()
743 		return AD7192_SYNC3_FILTER + oversampling_ratio - 1;  in ad7192_compute_f_order()
745 	return AD7192_SYNC4_FILTER + oversampling_ratio - 1;  in ad7192_compute_f_order()
752 	sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);  in ad7192_get_f_order()
753 	chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);  in ad7192_get_f_order()
763 	return DIV_ROUND_CLOSEST(st->fclk,  in ad7192_compute_f_adc()
764 				 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));  in ad7192_compute_f_adc()
771 	return DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_f_adc()
772 				 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));  in ad7192_get_f_adc()
781 	st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);  in ad7192_update_filter_freq_avail()
784 	st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);  in ad7192_update_filter_freq_avail()
787 	st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024);  in ad7192_update_filter_freq_avail()
790 	st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024);  in ad7192_update_filter_freq_avail()
835 	for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) {  in ad7192_set_3db_filter_freq()
836 		diff_new = abs(freq - st->filter_freq_avail[i][0]);  in ad7192_set_3db_filter_freq()
845 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
847 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
850 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
852 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
855 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
857 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
860 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
862 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
866 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_3db_filter_freq()
870 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_3db_filter_freq()
879 	if (FIELD_GET(AD7192_CONF_CHOP, st->conf))  in ad7192_get_3db_filter_freq()
881 	if (FIELD_GET(AD7192_MODE_SINC3, st->mode))  in ad7192_get_3db_filter_freq()
894 	bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);  in ad7192_read_raw()
895 	u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);  in ad7192_read_raw()
901 		switch (chan->type) {  in ad7192_read_raw()
903 			mutex_lock(&st->lock);  in ad7192_read_raw()
904 			*val = st->scale_avail[gain][0];  in ad7192_read_raw()
905 			*val2 = st->scale_avail[gain][1];  in ad7192_read_raw()
906 			mutex_unlock(&st->lock);  in ad7192_read_raw()
913 			return -EINVAL;  in ad7192_read_raw()
917 			*val = -(1 << (chan->scan_type.realbits - 1));  in ad7192_read_raw()
921 		switch (chan->type) {  in ad7192_read_raw()
924 			 * Only applies to pseudo-differential inputs.  in ad7192_read_raw()
927 			if (st->aincom_mv && !chan->differential)  in ad7192_read_raw()
928 				*val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO,  in ad7192_read_raw()
929 							      st->scale_avail[gain][1]);  in ad7192_read_raw()
933 			*val -= 273 * ad7192_get_temp_scale(unipolar);  in ad7192_read_raw()
936 			return -EINVAL;  in ad7192_read_raw()
946 		*val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];  in ad7192_read_raw()
950 	return -EINVAL;  in ad7192_read_raw()
967 	mutex_lock(&st->lock);  in ad7192_write_raw()
971 		ret = -EINVAL;  in ad7192_write_raw()
972 		for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)  in ad7192_write_raw()
973 			if (val2 == st->scale_avail[i][1]) {  in ad7192_write_raw()
975 				tmp = st->conf;  in ad7192_write_raw()
976 				st->conf &= ~AD7192_CONF_GAIN_MASK;  in ad7192_write_raw()
977 				st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);  in ad7192_write_raw()
978 				if (tmp == st->conf)  in ad7192_write_raw()
980 				ad_sd_write_reg(&st->sd, AD7192_REG_CONF,  in ad7192_write_raw()
981 						3, st->conf);  in ad7192_write_raw()
988 			ret = -EINVAL;  in ad7192_write_raw()
992 		div = st->fclk / (val * ad7192_get_f_order(st) * 1024);  in ad7192_write_raw()
994 			ret = -EINVAL;  in ad7192_write_raw()
998 		st->mode &= ~AD7192_MODE_RATE_MASK;  in ad7192_write_raw()
999 		st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);  in ad7192_write_raw()
1000 		ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_write_raw()
1007 		ret = -EINVAL;  in ad7192_write_raw()
1008 		for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++)  in ad7192_write_raw()
1009 			if (val == st->oversampling_ratio_avail[i]) {  in ad7192_write_raw()
1011 				tmp = st->mode;  in ad7192_write_raw()
1012 				st->mode &= ~AD7192_MODE_AVG_MASK;  in ad7192_write_raw()
1013 				st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);  in ad7192_write_raw()
1014 				if (tmp == st->mode)  in ad7192_write_raw()
1016 				ad_sd_write_reg(&st->sd, AD7192_REG_MODE,  in ad7192_write_raw()
1017 						3, st->mode);  in ad7192_write_raw()
1023 		ret = -EINVAL;  in ad7192_write_raw()
1026 	mutex_unlock(&st->lock);  in ad7192_write_raw()
1047 		return -EINVAL;  in ad7192_write_raw_get_fmt()
1060 		*vals = (int *)st->scale_avail;  in ad7192_read_avail()
1063 		*length = ARRAY_SIZE(st->scale_avail) * 2;  in ad7192_read_avail()
1067 		*vals = (int *)st->filter_freq_avail;  in ad7192_read_avail()
1069 		*length = ARRAY_SIZE(st->filter_freq_avail) * 2;  in ad7192_read_avail()
1073 		*vals = (int *)st->oversampling_ratio_avail;  in ad7192_read_avail()
1075 		*length = ARRAY_SIZE(st->oversampling_ratio_avail);  in ad7192_read_avail()
1080 	return -EINVAL;  in ad7192_read_avail()
1086 	u32 conf = st->conf;  in ad7192_update_scan_mode()
1094 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);  in ad7192_update_scan_mode()
1098 	st->conf = conf;  in ad7192_update_scan_mode()
1135 		.differential = ((_channel2) == -1 ? 0 : 1), \
1165 	__AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1169 	__AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1180 	AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1219 	struct device *dev = indio_dev->dev.parent;  in ad7194_parse_channels()
1231 		return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",  in ad7194_parse_channels()
1239 		return -ENOMEM;  in ad7194_parse_channels()
1241 	indio_dev->channels = ad7194_channels;  in ad7194_parse_channels()
1242 	indio_dev->num_channels = num_channels;  in ad7194_parse_channels()
1245 		ret = fwnode_property_read_u32_array(child, "diff-channels",  in ad7194_parse_channels()
1249 				return dev_err_probe(dev, -EINVAL,  in ad7194_parse_channels()
1254 				return dev_err_probe(dev, -EINVAL,  in ad7194_parse_channels()
1259 			ad7194_channels->scan_index = index++;  in ad7194_parse_channels()
1260 			ad7194_channels->channel = ain[0];  in ad7194_parse_channels()
1261 			ad7194_channels->channel2 = ain[1];  in ad7194_parse_channels()
1262 			ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]);  in ad7194_parse_channels()
1264 			ret = fwnode_property_read_u32(child, "single-channel",  in ad7194_parse_channels()
1271 				return dev_err_probe(dev, -EINVAL,  in ad7194_parse_channels()
1276 			ad7194_channels->scan_index = index++;  in ad7194_parse_channels()
1277 			ad7194_channels->channel = ain[0];  in ad7194_parse_channels()
1278 			ad7194_channels->address = AD7194_CH(ain[0]);  in ad7194_parse_channels()
1284 	ad7194_channels->scan_index = index++;  in ad7194_parse_channels()
1285 	ad7194_channels->address = AD7194_CH_TEMP;  in ad7194_parse_channels()
1289 	ad7194_channels->scan_index = index;  in ad7194_parse_channels()
1338 	struct device *dev = &spi->dev;  in ad7192_probe()
1343 	if (!spi->irq)  in ad7192_probe()
1344 		return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n");  in ad7192_probe()
1348 		return -ENOMEM;  in ad7192_probe()
1352 	mutex_init(&st->lock);  in ad7192_probe()
1360 	if (ret < 0 && ret != -ENODEV)  in ad7192_probe()
1363 	st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI;  in ad7192_probe()
1367 	if (ret == -ENODEV || ret == -EINVAL) {  in ad7192_probe()
1371 		 * We get -EINVAL if avdd is a supply with unknown voltage. We  in ad7192_probe()
1382 	avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI;  in ad7192_probe()
1389 	 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable.  in ad7192_probe()
1393 	if (ret == -ENODEV) {  in ad7192_probe()
1395 			return dev_err_probe(dev, -ENODEV,  in ad7192_probe()
1401 	st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI;  in ad7192_probe()
1403 	st->chip_info = spi_get_device_match_data(spi);  in ad7192_probe()
1404 	if (!st->chip_info)  in ad7192_probe()
1405 		return -ENODEV;  in ad7192_probe()
1407 	indio_dev->name = st->chip_info->name;  in ad7192_probe()
1408 	indio_dev->modes = INDIO_DIRECT_MODE;  in ad7192_probe()
1409 	indio_dev->info = st->chip_info->info;  in ad7192_probe()
1410 	if (st->chip_info->parse_channels) {  in ad7192_probe()
1411 		ret = st->chip_info->parse_channels(indio_dev);  in ad7192_probe()
1415 		indio_dev->channels = st->chip_info->channels;  in ad7192_probe()
1416 		indio_dev->num_channels = st->chip_info->num_channels;  in ad7192_probe()
1419 	ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info);  in ad7192_probe()