Lines Matching +full:400 +full:ns

173 		 * To be as close as possible to 400 kHz, the parent clk  in stm32f4_i2c_set_periph_clk_freq()
200 	 * In standard mode, the maximum allowed SCL rise time is 1000 ns.  in stm32f4_i2c_set_rise_time()
202 	 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be  in stm32f4_i2c_set_rise_time()
203 	 * programmed with 0x9. (1000 ns / 125 ns + 1)  in stm32f4_i2c_set_rise_time()
206 	 * In fast mode, the maximum allowed SCL rise time is 300 ns.  in stm32f4_i2c_set_rise_time()
208 	 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be  in stm32f4_i2c_set_rise_time()
209 	 * programmed with 0x3. (300 ns / 125 ns + 1)  in stm32f4_i2c_set_rise_time()
239 		 * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns  in stm32f4_i2c_set_speed_mode()
240 		 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached  in stm32f4_i2c_set_speed_mode()
250 		 * frequencies we are not able to reach 400 kHz.  in stm32f4_i2c_set_speed_mode()
254 		 * So, CCR = I2C parent rate / (400 kHz * 3)  in stm32f4_i2c_set_speed_mode()
258 		 * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns  in stm32f4_i2c_set_speed_mode()
259 		 * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns  in stm32f4_i2c_set_speed_mode()
260 		 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached  in stm32f4_i2c_set_speed_mode()