541 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)  in mtk_i2c_readw()  function
559 	intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);  in mtk_i2c_init_hw()
949 		mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),  in i2c_dump_register()
950 		mtk_i2c_readw(i2c, OFFSET_INTR_MASK));  in i2c_dump_register()
952 		mtk_i2c_readw(i2c, OFFSET_INTR_STAT),  in i2c_dump_register()
953 		mtk_i2c_readw(i2c, OFFSET_CONTROL));  in i2c_dump_register()
955 		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),  in i2c_dump_register()
956 		mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));  in i2c_dump_register()
958 		mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),  in i2c_dump_register()
959 		mtk_i2c_readw(i2c, OFFSET_TIMING));  in i2c_dump_register()
961 		mtk_i2c_readw(i2c, OFFSET_START),  in i2c_dump_register()
962 		mtk_i2c_readw(i2c, OFFSET_EXT_CONF));  in i2c_dump_register()
964 		mtk_i2c_readw(i2c, OFFSET_HS),  in i2c_dump_register()
965 		mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));  in i2c_dump_register()
967 		mtk_i2c_readw(i2c, OFFSET_DCM_EN),  in i2c_dump_register()
968 		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));  in i2c_dump_register()
970 		mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),  in i2c_dump_register()
971 		mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));  in i2c_dump_register()
973 		mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),  in i2c_dump_register()
974 		mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));  in i2c_dump_register()
977 			mtk_i2c_readw(i2c, OFFSET_LTIMING),  in i2c_dump_register()
978 			mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));  in i2c_dump_register()
1042 	control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &  in mtk_i2c_do_transfer()
1312 	intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);  in mtk_i2c_irq()