183 	 * yet. So we have to wait for TXCOMP or NACK bits to be set into the  in at91_twi_write_data_dma_callback()
185 	 * transfer is completed. The NACK interrupt has already been enabled,  in at91_twi_write_data_dma_callback()
425 	 * When a NACK condition is detected, the I2C controller sets the NACK,  in atmel_twi_interrupt()
428 	 * 1 - Handling NACK errors with CPU write transfer.  in atmel_twi_interrupt()
432 	 * transfer and the I2C slave is likely to reply by another NACK.  in atmel_twi_interrupt()
434 	 * 2 - Handling NACK errors with DMA write transfer.  in atmel_twi_interrupt()
444 	 * is likely to reply by another NACK.  in atmel_twi_interrupt()
446 	 * the first NACK before the I2C controller detects the second NACK and  in atmel_twi_interrupt()
447 	 * sets once again the NACK bit into the SR.  in atmel_twi_interrupt()
448 	 * When handling the first NACK, this interrupt handler disables the I2C  in atmel_twi_interrupt()
449 	 * controller interruptions, especially the NACK interrupt.  in atmel_twi_interrupt()
450 	 * Hence, the NACK bit is pending into the SR. This is why we should  in atmel_twi_interrupt()
456 	 * When a NACK condition is detected, the I2C controller also locks the  in atmel_twi_interrupt()
459 	 * this data actually won't go on the I2C bus hence a second NACK is not  in atmel_twi_interrupt()
488 	 * Consequently, we should enable NACK interrupt rather than TXCOMP to  in at91_do_twi_transfer()
491 	 * Whenever the slave doesn't acknowledge a byte, the LOCK, NACK and  in at91_do_twi_transfer()
494 	 * controller from sending new data on the i2c bus after a NACK  in at91_do_twi_transfer()
502 	 * read: the TXCOMP bit is clear but NACK bit is still set. The driver  in at91_do_twi_transfer()
531 	/* Clear pending interrupts, such as NACK. */  in at91_do_twi_transfer()
599 		dev_dbg(dev->dev, "received nack\n");  in at91_do_twi_transfer()