Lines Matching +full:dma +full:- +full:channel +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include "intel-thc-dev.h"
11 #include "intel-thc-dma.h"
12 #include "intel-thc-hw.h"
19 if (!dma_config->is_enabled) in dma_set_prd_base_addr()
25 regmap_write(dev->thc_regmap, dma_config->prd_base_addr_high, addr_high); in dma_set_prd_base_addr()
26 regmap_write(dev->thc_regmap, dma_config->prd_base_addr_low, addr_low); in dma_set_prd_base_addr()
32 u32 ctrl, mask, mbits, data, offset; in dma_set_start_bit() local
34 if (!dma_config->is_enabled) in dma_set_start_bit()
37 switch (dma_config->dma_channel) { in dma_set_start_bit()
40 if (dma_config->dma_channel == THC_RXDMA2) { in dma_set_start_bit()
43 mask = THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_DATA_VAL; in dma_set_start_bit()
44 regmap_write_bits(dev->thc_regmap, in dma_set_start_bit()
45 THC_M_PRT_DEVINT_CFG_1_OFFSET, mask, mbits); in dma_set_start_bit()
54 mask = THC_M_PRT_READ_DMA_CNTRL_TPCWP | mbits; in dma_set_start_bit()
55 mask |= THC_M_PRT_READ_DMA_CNTRL_INT_SW_DMA_EN; in dma_set_start_bit()
57 offset = dma_config->dma_channel == THC_RXDMA1 ? in dma_set_start_bit()
59 regmap_write_bits(dev->thc_regmap, offset, mask, ctrl); in dma_set_start_bit()
68 mask = THC_M_PRT_READ_DMA_CNTRL_TPCWP | mbits; in dma_set_start_bit()
70 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_SW_OFFSET, in dma_set_start_bit()
71 mask, ctrl); in dma_set_start_bit()
75 regmap_write_bits(dev->thc_regmap, THC_M_PRT_WRITE_INT_STS_OFFSET, in dma_set_start_bit()
80 if (dev->dma_ctx->use_write_interrupts) in dma_set_start_bit()
86 mask = THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_DMACPL | in dma_set_start_bit()
88 regmap_write_bits(dev->thc_regmap, THC_M_PRT_WRITE_DMA_CNTRL_OFFSET, in dma_set_start_bit()
89 mask, data); in dma_set_start_bit()
100 u32 ctrl, mask; in dma_set_prd_control() local
102 if (!dma_config->is_enabled) in dma_set_prd_control()
105 if (dma_config->dma_channel == THC_TXDMA) { in dma_set_prd_control()
106 mask = THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_PTEC; in dma_set_prd_control()
109 mask = THC_M_PRT_RPRD_CNTRL_PTEC | THC_M_PRT_RPRD_CNTRL_PCD; in dma_set_prd_control()
114 regmap_write_bits(dev->thc_regmap, dma_config->prd_cntrl, mask, ctrl); in dma_set_prd_control()
120 u32 mask; in dma_clear_prd_control() local
122 if (!dma_config->is_enabled) in dma_clear_prd_control()
125 if (dma_config->dma_channel == THC_TXDMA) in dma_clear_prd_control()
126 mask = THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_PTEC; in dma_clear_prd_control()
128 mask = THC_M_PRT_RPRD_CNTRL_PTEC | THC_M_PRT_RPRD_CNTRL_PCD; in dma_clear_prd_control()
130 regmap_write_bits(dev->thc_regmap, dma_config->prd_cntrl, mask, 0); in dma_clear_prd_control()
138 regmap_read(dev->thc_regmap, dma_config->dma_cntrl, &ctrl); in dma_get_read_pointer()
141 dev_dbg(dev->dev, "THC_M_PRT_READ_DMA_CNTRL 0x%x offset 0x%x TPCRP 0x%x\n", in dma_get_read_pointer()
142 ctrl, dma_config->dma_cntrl, read_pointer); in dma_get_read_pointer()
152 regmap_read(dev->thc_regmap, dma_config->dma_cntrl, &ctrl); in dma_get_write_pointer()
155 dev_dbg(dev->dev, "THC_M_PRT_READ_DMA_CNTRL 0x%x offset 0x%x TPCWP 0x%x\n", in dma_get_write_pointer()
156 ctrl, dma_config->dma_cntrl, write_pointer); in dma_get_write_pointer()
164 u32 ctrl, mask; in dma_set_write_pointer() local
166 mask = THC_M_PRT_READ_DMA_CNTRL_TPCWP; in dma_set_write_pointer()
168 regmap_write_bits(dev->thc_regmap, dma_config->dma_cntrl, mask, ctrl); in dma_set_write_pointer()
174 return dma_config->max_packet_size; in dma_get_max_packet_size()
181 dma_config->max_packet_size = ALIGN(size, SZ_4K); in dma_set_max_packet_size()
182 dma_config->is_enabled = true; in dma_set_max_packet_size()
194 prd_tbl = &config->prd_tbls[ind]; in thc_copy_one_sgl_to_prd()
196 for_each_sg(config->sgls[ind], sg, config->sgls_nent[ind], j) { in thc_copy_one_sgl_to_prd()
197 prd_tbl->entries[j].dest_addr = in thc_copy_one_sgl_to_prd()
199 prd_tbl->entries[j].len = sg_dma_len(sg); in thc_copy_one_sgl_to_prd()
200 prd_tbl->entries[j].hw_status = 0; in thc_copy_one_sgl_to_prd()
201 prd_tbl->entries[j].end_of_prd = 0; in thc_copy_one_sgl_to_prd()
206 prd_tbl->entries[j - 1].end_of_prd = 1; in thc_copy_one_sgl_to_prd()
214 memset(config->prd_tbls, 0, array_size(PRD_TABLE_SIZE, config->prd_tbl_num)); in thc_copy_sgls_to_prd()
216 for (i = 0; i < config->prd_tbl_num; i++) in thc_copy_sgls_to_prd()
224 size_t prd_tbls_size = array_size(PRD_TABLE_SIZE, config->prd_tbl_num); in setup_dma_buffers()
231 if (!config->is_enabled) in setup_dma_buffers()
234 memset(config->sgls, 0, sizeof(config->sgls)); in setup_dma_buffers()
235 memset(config->sgls_nent, 0, sizeof(config->sgls_nent)); in setup_dma_buffers()
237 cpu_addr = dma_alloc_coherent(dev->dev, prd_tbls_size, in setup_dma_buffers()
240 return -ENOMEM; in setup_dma_buffers()
242 config->prd_tbls = cpu_addr; in setup_dma_buffers()
243 config->prd_tbls_dma_handle = dma_handle; in setup_dma_buffers()
247 /* Allocate and map the scatter-gather lists, one for each PRD table */ in setup_dma_buffers()
248 for (i = 0; i < config->prd_tbl_num; i++) { in setup_dma_buffers()
249 config->sgls[i] = sgl_alloc(buf_sz, GFP_KERNEL, &nent); in setup_dma_buffers()
250 if (!config->sgls[i] || nent > PRD_ENTRIES_NUM) { in setup_dma_buffers()
251 dev_err_once(dev->dev, "sgl_alloc (%uth) failed, nent %u\n", in setup_dma_buffers()
253 return -ENOMEM; in setup_dma_buffers()
255 count = dma_map_sg(dev->dev, config->sgls[i], nent, dir); in setup_dma_buffers()
257 config->sgls_nent[i] = count; in setup_dma_buffers()
267 /* Stop all DMA channels and reset DMA read pointers */ in thc_reset_dma_settings()
268 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_1_OFFSET, in thc_reset_dma_settings()
270 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_2_OFFSET, in thc_reset_dma_settings()
272 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_SW_OFFSET, in thc_reset_dma_settings()
274 regmap_write_bits(dev->thc_regmap, THC_M_PRT_WRITE_DMA_CNTRL_OFFSET, in thc_reset_dma_settings()
277 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_1_OFFSET, in thc_reset_dma_settings()
280 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_2_OFFSET, in thc_reset_dma_settings()
283 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_SW_OFFSET, in thc_reset_dma_settings()
291 size_t prd_tbls_size = array_size(PRD_TABLE_SIZE, config->prd_tbl_num); in release_dma_buffers()
294 if (!config->is_enabled) in release_dma_buffers()
297 for (i = 0; i < config->prd_tbl_num; i++) { in release_dma_buffers()
298 if (!config->sgls[i] | !config->sgls_nent[i]) in release_dma_buffers()
301 dma_unmap_sg(dev->dev, config->sgls[i], in release_dma_buffers()
302 config->sgls_nent[i], in release_dma_buffers()
303 config->dir); in release_dma_buffers()
305 sgl_free(config->sgls[i]); in release_dma_buffers()
306 config->sgls[i] = NULL; in release_dma_buffers()
309 memset(config->prd_tbls, 0, prd_tbls_size); in release_dma_buffers()
311 if (config->prd_tbls) { in release_dma_buffers()
312 dma_free_coherent(dev->dev, prd_tbls_size, config->prd_tbls, in release_dma_buffers()
313 config->prd_tbls_dma_handle); in release_dma_buffers()
314 config->prd_tbls = NULL; in release_dma_buffers()
315 config->prd_tbls_dma_handle = 0; in release_dma_buffers()
323 dma_ctx = devm_kzalloc(dev->dev, sizeof(*dma_ctx), GFP_KERNEL); in thc_dma_init()
327 dev->dma_ctx = dma_ctx; in thc_dma_init()
329 dma_ctx->dma_config[THC_RXDMA1].dma_channel = THC_RXDMA1; in thc_dma_init()
330 dma_ctx->dma_config[THC_RXDMA2].dma_channel = THC_RXDMA2; in thc_dma_init()
331 dma_ctx->dma_config[THC_TXDMA].dma_channel = THC_TXDMA; in thc_dma_init()
332 dma_ctx->dma_config[THC_SWDMA].dma_channel = THC_SWDMA; in thc_dma_init()
334 dma_ctx->dma_config[THC_RXDMA1].dir = DMA_FROM_DEVICE; in thc_dma_init()
335 dma_ctx->dma_config[THC_RXDMA2].dir = DMA_FROM_DEVICE; in thc_dma_init()
336 dma_ctx->dma_config[THC_TXDMA].dir = DMA_TO_DEVICE; in thc_dma_init()
337 dma_ctx->dma_config[THC_SWDMA].dir = DMA_FROM_DEVICE; in thc_dma_init()
339 dma_ctx->dma_config[THC_RXDMA1].prd_tbl_num = PRD_TABLES_NUM; in thc_dma_init()
340 dma_ctx->dma_config[THC_RXDMA2].prd_tbl_num = PRD_TABLES_NUM; in thc_dma_init()
341 dma_ctx->dma_config[THC_TXDMA].prd_tbl_num = 1; in thc_dma_init()
342 dma_ctx->dma_config[THC_SWDMA].prd_tbl_num = 1; in thc_dma_init()
344 dma_ctx->dma_config[THC_RXDMA1].prd_base_addr_high = THC_M_PRT_RPRD_BA_HI_1_OFFSET; in thc_dma_init()
345 dma_ctx->dma_config[THC_RXDMA2].prd_base_addr_high = THC_M_PRT_RPRD_BA_HI_2_OFFSET; in thc_dma_init()
346 dma_ctx->dma_config[THC_TXDMA].prd_base_addr_high = THC_M_PRT_WPRD_BA_HI_OFFSET; in thc_dma_init()
347 dma_ctx->dma_config[THC_SWDMA].prd_base_addr_high = THC_M_PRT_RPRD_BA_HI_SW_OFFSET; in thc_dma_init()
349 dma_ctx->dma_config[THC_RXDMA1].prd_base_addr_low = THC_M_PRT_RPRD_BA_LOW_1_OFFSET; in thc_dma_init()
350 dma_ctx->dma_config[THC_RXDMA2].prd_base_addr_low = THC_M_PRT_RPRD_BA_LOW_2_OFFSET; in thc_dma_init()
351 dma_ctx->dma_config[THC_TXDMA].prd_base_addr_low = THC_M_PRT_WPRD_BA_LOW_OFFSET; in thc_dma_init()
352 dma_ctx->dma_config[THC_SWDMA].prd_base_addr_low = THC_M_PRT_RPRD_BA_LOW_SW_OFFSET; in thc_dma_init()
354 dma_ctx->dma_config[THC_RXDMA1].prd_cntrl = THC_M_PRT_RPRD_CNTRL_1_OFFSET; in thc_dma_init()
355 dma_ctx->dma_config[THC_RXDMA2].prd_cntrl = THC_M_PRT_RPRD_CNTRL_2_OFFSET; in thc_dma_init()
356 dma_ctx->dma_config[THC_TXDMA].prd_cntrl = THC_M_PRT_WRITE_DMA_CNTRL_OFFSET; in thc_dma_init()
357 dma_ctx->dma_config[THC_SWDMA].prd_cntrl = THC_M_PRT_RPRD_CNTRL_SW_OFFSET; in thc_dma_init()
359 dma_ctx->dma_config[THC_RXDMA1].dma_cntrl = THC_M_PRT_READ_DMA_CNTRL_1_OFFSET; in thc_dma_init()
360 dma_ctx->dma_config[THC_RXDMA2].dma_cntrl = THC_M_PRT_READ_DMA_CNTRL_2_OFFSET; in thc_dma_init()
361 dma_ctx->dma_config[THC_TXDMA].dma_cntrl = THC_M_PRT_WRITE_DMA_CNTRL_OFFSET; in thc_dma_init()
362 dma_ctx->dma_config[THC_SWDMA].dma_cntrl = THC_M_PRT_READ_DMA_CNTRL_SW_OFFSET; in thc_dma_init()
364 /* Enable write DMA completion interrupt by default */ in thc_dma_init()
365 dma_ctx->use_write_interrupts = 1; in thc_dma_init()
371 * thc_dma_set_max_packet_sizes - Set max packet sizes for all DMA engines
377 * @mps_swdma: Software DMA max packet size
379 * If mps is not 0, it means the corresponding DMA channel is used, then set
380 * the flag to turn on this channel.
388 if (!dev->dma_ctx) { in thc_dma_set_max_packet_sizes()
389 dev_err_once(dev->dev, in thc_dma_set_max_packet_sizes()
390 "Cannot set max packet sizes because DMA context is NULL!\n"); in thc_dma_set_max_packet_sizes()
391 return -EINVAL; in thc_dma_set_max_packet_sizes()
394 dma_set_max_packet_size(dev, mps_read1, &dev->dma_ctx->dma_config[THC_RXDMA1]); in thc_dma_set_max_packet_sizes()
395 dma_set_max_packet_size(dev, mps_read2, &dev->dma_ctx->dma_config[THC_RXDMA2]); in thc_dma_set_max_packet_sizes()
396 dma_set_max_packet_size(dev, mps_write, &dev->dma_ctx->dma_config[THC_TXDMA]); in thc_dma_set_max_packet_sizes()
397 dma_set_max_packet_size(dev, mps_swdma, &dev->dma_ctx->dma_config[THC_SWDMA]); in thc_dma_set_max_packet_sizes()
404 * thc_dma_allocate - Allocate DMA buffers for all DMA engines
415 ret = setup_dma_buffers(dev, &dev->dma_ctx->dma_config[chan], in thc_dma_allocate()
416 dev->dma_ctx->dma_config[chan].dir); in thc_dma_allocate()
418 dev_err_once(dev->dev, "DMA setup failed for DMA channel %d\n", chan); in thc_dma_allocate()
426 while (chan--) in thc_dma_allocate()
427 release_dma_buffers(dev, &dev->dma_ctx->dma_config[chan]); in thc_dma_allocate()
434 * thc_dma_release - Release DMA buffers for all DMA engines
443 release_dma_buffers(dev, &dev->dma_ctx->dma_config[chan]); in thc_dma_release()
452 return -EMSGSIZE; in calc_prd_entries_num()
463 mes_len += prd_tbl->entries[j].len; in calc_message_len()
464 if (prd_tbl->entries[j].end_of_prd) in calc_message_len()
474 * thc_dma_configure - Configure DMA settings for all DMA engines
482 struct thc_dma_context *dma_ctx = dev->dma_ctx; in thc_dma_configure()
488 dev_err_once(dev->dev, "Cannot do DMA configure because DMA context is NULL\n"); in thc_dma_configure()
489 return -EINVAL; in thc_dma_configure()
494 dma_ctx->dma_config[chan].prd_tbls_dma_handle, in thc_dma_configure()
495 &dma_ctx->dma_config[chan]); in thc_dma_configure()
497 dma_set_prd_control(dev, PRD_ENTRIES_NUM - 1, in thc_dma_configure()
498 dma_ctx->dma_config[chan].prd_tbl_num - 1, in thc_dma_configure()
499 &dma_ctx->dma_config[chan]); in thc_dma_configure()
502 /* Start read2 DMA engine */ in thc_dma_configure()
503 dma_set_start_bit(dev, &dma_ctx->dma_config[THC_RXDMA2]); in thc_dma_configure()
505 dev_dbg(dev->dev, "DMA configured successfully!\n"); in thc_dma_configure()
512 * thc_dma_unconfigure - Unconfigure DMA settings for all DMA engines
521 dma_set_prd_base_addr(dev, 0, &dev->dma_ctx->dma_config[chan]); in thc_dma_unconfigure()
522 dma_clear_prd_control(dev, &dev->dma_ctx->dma_config[chan]); in thc_dma_unconfigure()
525 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_1_OFFSET, in thc_dma_unconfigure()
528 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_2_OFFSET, in thc_dma_unconfigure()
533 static int thc_wait_for_dma_pause(struct thc_device *dev, enum thc_dma_channel channel) in thc_wait_for_dma_pause() argument
538 ctrl_reg = (channel == THC_RXDMA1) ? THC_M_PRT_READ_DMA_CNTRL_1_OFFSET : in thc_wait_for_dma_pause()
539 ((channel == THC_RXDMA2) ? THC_M_PRT_READ_DMA_CNTRL_2_OFFSET : in thc_wait_for_dma_pause()
542 regmap_write_bits(dev->thc_regmap, ctrl_reg, THC_M_PRT_READ_DMA_CNTRL_START, 0); in thc_wait_for_dma_pause()
544 sts_reg = (channel == THC_RXDMA1) ? THC_M_PRT_READ_DMA_INT_STS_1_OFFSET : in thc_wait_for_dma_pause()
545 ((channel == THC_RXDMA2) ? THC_M_PRT_READ_DMA_INT_STS_2_OFFSET : in thc_wait_for_dma_pause()
548 ret = regmap_read_poll_timeout(dev->thc_regmap, sts_reg, sts, in thc_wait_for_dma_pause()
554 dev_err_once(dev->dev, in thc_wait_for_dma_pause()
555 "Timeout while waiting for DMA %d stop\n", channel); in thc_wait_for_dma_pause()
571 if (prd_table_index >= read_config->prd_tbl_num) { in read_dma_buffer()
572 dev_err_once(dev->dev, "PRD table index %d too big\n", prd_table_index); in read_dma_buffer()
573 return -EINVAL; in read_dma_buffer()
576 prd_tbl = &read_config->prd_tbls[prd_table_index]; in read_dma_buffer()
578 if (mes_len > read_config->max_packet_size) { in read_dma_buffer()
579 dev_err(dev->dev, in read_dma_buffer()
581 mes_len, read_config->max_packet_size); in read_dma_buffer()
582 return -EMSGSIZE; in read_dma_buffer()
585 sg = read_config->sgls[prd_table_index]; in read_dma_buffer()
588 dev_err_once(dev->dev, "Copied %zu bytes instead of requested %zu\n", in read_dma_buffer()
590 return -EIO; in read_dma_buffer()
635 dev_err_once(dev->dev, "read DMA buffer failed %d\n", status); in thc_dma_read()
636 return -EIO; in thc_dma_read()
660 * thc_rxdma_read - Read data from RXDMA buffer
676 dma_config = &dev->dma_ctx->dma_config[dma_channel]; in thc_rxdma_read()
678 if (!dma_config->is_enabled) { in thc_rxdma_read()
679 dev_err_once(dev->dev, "The DMA channel %d is not enabled", dma_channel); in thc_rxdma_read()
680 return -EINVAL; in thc_rxdma_read()
684 dev_err(dev->dev, "Invalid input parameters, read_buff %p, read_len %p\n", in thc_rxdma_read()
686 return -EINVAL; in thc_rxdma_read()
690 dev_err(dev->dev, "Unsupported DMA channel for RxDMA read, %d\n", dma_channel); in thc_rxdma_read()
691 return -EINVAL; in thc_rxdma_read()
703 u32 mask, val, data0 = 0, data1 = 0; in thc_swdma_read_start() local
711 return -EIO; in thc_swdma_read_start()
715 mask = THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_WBC | in thc_swdma_read_start()
719 regmap_write_bits(dev->thc_regmap, THC_M_PRT_RPRD_CNTRL_SW_OFFSET, in thc_swdma_read_start()
720 mask, val); in thc_swdma_read_start()
723 mask = THC_M_PRT_SW_DMA_PRD_TABLE_LEN_THC_M_PRT_SW_DMA_PRD_TABLE_LEN; in thc_swdma_read_start()
726 regmap_write_bits(dev->thc_regmap, THC_M_PRT_SW_DMA_PRD_TABLE_LEN_OFFSET, in thc_swdma_read_start()
727 mask, val); in thc_swdma_read_start()
734 regmap_write(dev->thc_regmap, THC_M_PRT_SW_SEQ_DATA0_ADDR_OFFSET, data0); in thc_swdma_read_start()
737 regmap_write(dev->thc_regmap, THC_M_PRT_SW_SEQ_DATA0_ADDR_OFFSET, data0); in thc_swdma_read_start()
739 for (int i = 0; i < write_len - sizeof(u32); i++) in thc_swdma_read_start()
742 regmap_write(dev->thc_regmap, THC_M_PRT_SW_SEQ_DATA1_OFFSET, data1); in thc_swdma_read_start()
744 dma_set_start_bit(dev, &dev->dma_ctx->dma_config[THC_SWDMA]); in thc_swdma_read_start()
759 dma_set_start_bit(dev, &dev->dma_ctx->dma_config[THC_RXDMA2]); in thc_swdma_read_completion()
767 * thc_swdma_read - Use software DMA to read data from touch device
783 if (!(&dev->dma_ctx->dma_config[THC_SWDMA])->is_enabled) { in thc_swdma_read()
784 dev_err_once(dev->dev, "The SWDMA channel is not enabled"); in thc_swdma_read()
785 return -EINVAL; in thc_swdma_read()
789 dev_err(dev->dev, "Invalid input parameters, read_buff %p, read_len %p\n", in thc_swdma_read()
791 return -EINVAL; in thc_swdma_read()
794 if (mutex_lock_interruptible(&dev->thc_bus_lock)) in thc_swdma_read()
795 return -EINTR; in thc_swdma_read()
797 dev->swdma_done = false; in thc_swdma_read()
803 ret = wait_event_interruptible_timeout(dev->swdma_complete_wait, dev->swdma_done, 1 * HZ); in thc_swdma_read()
804 if (ret <= 0 || !dev->swdma_done) { in thc_swdma_read()
805 dev_err_once(dev->dev, "timeout for waiting SWDMA completion\n"); in thc_swdma_read()
806 ret = -ETIMEDOUT; in thc_swdma_read()
810 ret = thc_dma_read(dev, &dev->dma_ctx->dma_config[THC_SWDMA], read_buff, read_len, NULL); in thc_swdma_read()
817 mutex_unlock(&dev->thc_bus_lock); in thc_swdma_read()
825 struct thc_dma_configuration *write_config = &dev->dma_ctx->dma_config[THC_TXDMA]; in write_dma_buffer()
834 prd_tbl = &write_config->prd_tbls[0]; in write_dma_buffer()
837 dev_err(dev->dev, "Tx message length too big (%zu)\n", buf_len); in write_dma_buffer()
838 return -EOVERFLOW; in write_dma_buffer()
841 sg = write_config->sgls[0]; in write_dma_buffer()
844 dev_err_once(dev->dev, "Copied %zu bytes instead of requested %zu\n", in write_dma_buffer()
846 return -EIO; in write_dma_buffer()
849 prd_tbl = &write_config->prd_tbls[0]; in write_dma_buffer()
852 for_each_sg(write_config->sgls[0], sg, write_config->sgls_nent[0], i) { in write_dma_buffer()
854 dev_err_once(dev->dev, "SGList: zero address or length\n"); in write_dma_buffer()
855 return -EINVAL; in write_dma_buffer()
858 prd_tbl->entries[i].dest_addr = in write_dma_buffer()
862 prd_tbl->entries[i].len = len_left; in write_dma_buffer()
863 prd_tbl->entries[i].end_of_prd = 1; in write_dma_buffer()
867 prd_tbl->entries[i].len = sg_dma_len(sg); in write_dma_buffer()
868 prd_tbl->entries[i].end_of_prd = 0; in write_dma_buffer()
870 len_left -= sg_dma_len(sg); in write_dma_buffer()
886 if (dev->perf_limit > 0) { in thc_ensure_performance_limitations()
887 delay_usec = dev->perf_limit * 10; in thc_ensure_performance_limitations()
898 * thc_dma_write - Use TXDMA to write data to touch device
912 if (!(&dev->dma_ctx->dma_config[THC_TXDMA])->is_enabled) { in thc_dma_write()
913 dev_err_once(dev->dev, "The TxDMA channel is not enabled\n"); in thc_dma_write()
914 return -EINVAL; in thc_dma_write()
918 dev_err(dev->dev, "Invalid input parameters, buffer %p\n, buf_len %zu\n", in thc_dma_write()
920 return -EINVAL; in thc_dma_write()
923 regmap_read(dev->thc_regmap, THC_M_PRT_WRITE_INT_STS_OFFSET, &sts); in thc_dma_write()
925 dev_err_once(dev->dev, "THC TxDMA is till active and can't start again\n"); in thc_dma_write()
926 return -EBUSY; in thc_dma_write()
929 if (mutex_lock_interruptible(&dev->thc_bus_lock)) in thc_dma_write()
930 return -EINTR; in thc_dma_write()
932 regmap_read(dev->thc_regmap, THC_M_PRT_CONTROL_OFFSET, &ctrl); in thc_dma_write()
938 if (dev->perf_limit && !(ctrl & THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_HW_STS)) { in thc_dma_write()
946 dev->write_done = false; in thc_dma_write()
948 dma_set_start_bit(dev, &dev->dma_ctx->dma_config[THC_TXDMA]); in thc_dma_write()
950 ret = wait_event_interruptible_timeout(dev->write_complete_wait, dev->write_done, 1 * HZ); in thc_dma_write()
951 if (ret <= 0 || !dev->write_done) { in thc_dma_write()
952 dev_err_once(dev->dev, "timeout for waiting TxDMA completion\n"); in thc_dma_write()
953 ret = -ETIMEDOUT; in thc_dma_write()
958 mutex_unlock(&dev->thc_bus_lock); in thc_dma_write()
962 mutex_unlock(&dev->thc_bus_lock); in thc_dma_write()