29 	struct xe_tile *tile;  in tiles_fini()  local
32 	for_each_remote_tile(tile, xe, id)  in tiles_fini()
33 		tile->mmio.regs = NULL;  in tiles_fini()
37  * On multi-tile devices, partition the BAR space for MMIO on each tile,
39  * tile_mmio_size contains both the tile's 4MB register space, as well as
57 	struct xe_tile *tile;  in mmio_multi_tile_setup()  local
62 	 * Nothing to be done as tile 0 has already been setup earlier with the  in mmio_multi_tile_setup()
68 	/* Possibly override number of tile based on configuration register */  in mmio_multi_tile_setup()
75 		 * Although the per-tile mmio regs are not yet initialized, this  in mmio_multi_tile_setup()
76 		 * is fine as it's going to the root tile's mmio, that's  in mmio_multi_tile_setup()
89 			 * should be impossible with multi-tile for now:  in mmio_multi_tile_setup()
90 			 * multi-tile platform with standalone media doesn't  in mmio_multi_tile_setup()
98 	for_each_tile(tile, xe, id) {  in mmio_multi_tile_setup()
99 		tile->mmio.regs_size = SZ_4M;  in mmio_multi_tile_setup()
100 		tile->mmio.regs = regs;  in mmio_multi_tile_setup()
101 		tile->mmio.tile = tile;  in mmio_multi_tile_setup()
107  * On top of all the multi-tile MMIO space there can be a platform-dependent
108  * extension for each tile, resulting in a layout like below:
122  * Set up the tile[]->mmio_ext pointers/sizes.
127 	struct xe_tile *tile;  in mmio_extension_setup()  local
135 	for_each_tile(tile, xe, id) {  in mmio_extension_setup()
136 		tile->mmio_ext.regs_size = tile_mmio_ext_size;  in mmio_extension_setup()
137 		tile->mmio_ext.regs = regs;  in mmio_extension_setup()
138 		tile->mmio_ext.tile = tile;  in mmio_extension_setup()
171 	 * The first 16MB of the BAR, belong to the root tile, and include:  in xe_mmio_init()
181 	/* Setup first tile; other tiles (if present) will be setup later. */  in xe_mmio_init()
184 	root_tile->mmio.tile = root_tile;  in xe_mmio_init()
194 	if (mmio->tile->xe->info.platform != XE_LUNARLAKE)  in mmio_flush_pending_writes()
322 	xe_tile_assert(mmio->tile, reg_udw.addr == reg.addr + 0x4);  in xe_mmio_read64_2x32()
335 	drm_WARN(&mmio->tile->xe->drm, retries == 0,  in xe_mmio_read64_2x32()