45 	drm_WARN(&mmio->tile->xe->drm, 1,  in assert_iir_is_zero()
58 static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)  in unmask_and_enable()  argument
60 	struct xe_mmio *mmio = &tile->mmio;  in unmask_and_enable()
76 static void mask_and_disable(struct xe_tile *tile, u32 irqregs)  in mask_and_disable()  argument
78 	struct xe_mmio *mmio = &tile->mmio;  in mask_and_disable()
267 static struct xe_gt *pick_engine_gt(struct xe_tile *tile,  in pick_engine_gt()  argument
271 	struct xe_device *xe = tile_to_xe(tile);  in pick_engine_gt()
274 		return tile->primary_gt;  in pick_engine_gt()
279 		return tile->media_gt;  in pick_engine_gt()
285 			return tile->media_gt;  in pick_engine_gt()
291 		return tile->primary_gt;  in pick_engine_gt()
295 static void gt_irq_handler(struct xe_tile *tile,  in gt_irq_handler()  argument
299 	struct xe_device *xe = tile_to_xe(tile);  in gt_irq_handler()
300 	struct xe_mmio *mmio = &tile->mmio;  in gt_irq_handler()
324 			engine_gt = pick_engine_gt(tile, class, instance);  in gt_irq_handler()
347  * a "master tile" interrupt register.
352 	struct xe_tile *tile = xe_device_get_root_tile(xe);  in xelp_irq_handler()  local
366 	gt_irq_handler(tile, master_ctl, intr_dw, identity);  in xelp_irq_handler()
408  * a "master tile" interrupt register which must be consulted before the
414 	struct xe_tile *tile;  in dg1_irq_handler()  local
431 	for_each_tile(tile, xe, id) {  in dg1_irq_handler()
432 		struct xe_mmio *mmio = &tile->mmio;  in dg1_irq_handler()
434 		if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)  in dg1_irq_handler()
445 			drm_dbg(&tile_to_xe(tile)->drm,  in dg1_irq_handler()
452 		gt_irq_handler(tile, master_ctl, intr_dw, identity);  in dg1_irq_handler()
457 		 * the primary tile.  in dg1_irq_handler()
473 static void gt_irq_reset(struct xe_tile *tile)  in gt_irq_reset()  argument
475 	struct xe_mmio *mmio = &tile->mmio;  in gt_irq_reset()
477 	u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,  in gt_irq_reset()
479 	u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,  in gt_irq_reset()
507 	if ((tile->media_gt &&  in gt_irq_reset()
508 	     xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) ||  in gt_irq_reset()
509 	    tile_to_xe(tile)->info.has_heci_gscfi) {  in gt_irq_reset()
521 static void xelp_irq_reset(struct xe_tile *tile)  in xelp_irq_reset()  argument
523 	xelp_intr_disable(tile_to_xe(tile));  in xelp_irq_reset()
525 	gt_irq_reset(tile);  in xelp_irq_reset()
527 	if (IS_SRIOV_VF(tile_to_xe(tile)))  in xelp_irq_reset()
530 	mask_and_disable(tile, PCU_IRQ_OFFSET);  in xelp_irq_reset()
533 static void dg1_irq_reset(struct xe_tile *tile)  in dg1_irq_reset()  argument
535 	if (tile->id == 0)  in dg1_irq_reset()
536 		dg1_intr_disable(tile_to_xe(tile));  in dg1_irq_reset()
538 	gt_irq_reset(tile);  in dg1_irq_reset()
540 	if (IS_SRIOV_VF(tile_to_xe(tile)))  in dg1_irq_reset()
543 	mask_and_disable(tile, PCU_IRQ_OFFSET);  in dg1_irq_reset()
546 static void dg1_irq_reset_mstr(struct xe_tile *tile)  in dg1_irq_reset_mstr()  argument
548 	struct xe_mmio *mmio = &tile->mmio;  in dg1_irq_reset_mstr()
555 	struct xe_tile *tile;  in vf_irq_reset()  local
565 	for_each_tile(tile, xe, id) {  in vf_irq_reset()
567 			xe_memirq_reset(&tile->memirq);  in vf_irq_reset()
569 			gt_irq_reset(tile);  in vf_irq_reset()
575 	struct xe_tile *tile;  in xe_irq_reset()  local
582 		for_each_tile(tile, xe, id)  in xe_irq_reset()
583 			xe_memirq_reset(&tile->memirq);  in xe_irq_reset()
586 	for_each_tile(tile, xe, id) {  in xe_irq_reset()
588 			dg1_irq_reset(tile);  in xe_irq_reset()
590 			xelp_irq_reset(tile);  in xe_irq_reset()
593 	tile = xe_device_get_root_tile(xe);  in xe_irq_reset()
594 	mask_and_disable(tile, GU_MISC_IRQ_OFFSET);  in xe_irq_reset()
598 	 * The tile's top-level status register should be the last one  in xe_irq_reset()
603 		for_each_tile(tile, xe, id)  in xe_irq_reset()
604 			dg1_irq_reset_mstr(tile);  in xe_irq_reset()
610 	struct xe_tile *tile;  in vf_irq_postinstall()  local
613 	for_each_tile(tile, xe, id)  in vf_irq_postinstall()
615 			xe_memirq_postinstall(&tile->memirq);  in vf_irq_postinstall()
629 		struct xe_tile *tile;  in xe_irq_postinstall()  local
632 		for_each_tile(tile, xe, id)  in xe_irq_postinstall()
633 			xe_memirq_postinstall(&tile->memirq);  in xe_irq_postinstall()
640 	 * on the root tile.  in xe_irq_postinstall()
655 	struct xe_tile *tile;  in vf_mem_irq_handler()  local
661 	for_each_tile(tile, xe, id)  in vf_mem_irq_handler()
662 		xe_memirq_handler(&tile->memirq);  in vf_mem_irq_handler()
828 	struct xe_tile *tile;  in guc2host_irq_handler()  local
834 	for_each_tile(tile, xe, id)  in guc2host_irq_handler()
835 		xe_guc_irq_handler(&tile->primary_gt->uc.guc,  in guc2host_irq_handler()
848 	struct xe_tile *tile;  in xe_irq_msix_default_hwe_handler()  local
854 	for_each_tile(tile, xe, tile_id) {  in xe_irq_msix_default_hwe_handler()
855 		memirq = &tile->memirq;  in xe_irq_msix_default_hwe_handler()
860 			if (gt->tile != tile)  in xe_irq_msix_default_hwe_handler()