Lines Matching +full:11 +full:- +full:bit

1 /* SPDX-License-Identifier: MIT */
62 #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
64 /* 32-bit KLV structure as used by policy updates and others */
81 /* GUC_CTL_* - Parameters for loading the GuC */
83 #define GUC_LOG_VALID BIT(0)
84 #define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)
85 #define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)
86 #define GUC_LOG_LOG_ALLOC_UNITS BIT(3)
96 #define GUC_WA_GAM_CREDITS BIT(10)
97 #define GUC_WA_DUAL_QUEUE BIT(11)
98 #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
99 #define GUC_WA_CONTEXT_ISOLATION BIT(15)
100 #define GUC_WA_PRE_PARSER BIT(14)
101 #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
102 #define GUC_WA_POLLCS BIT(18)
103 #define GUC_WA_RENDER_RST_RC6_EXIT BIT(19)
104 #define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
105 #define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)
108 #define GUC_CTL_ENABLE_SLPC BIT(2)
109 #define GUC_CTL_ENABLE_LITE_RESTORE BIT(4)
110 #define GUC_CTL_DISABLE_SCHEDULER BIT(14)
138 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
195 u32 reserved[11];
211 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
213 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
214 XE_GUC_RECV_MSG_EXCEPTION = BIT(30),
220 #define ACCESS_COUNTER_TYPE BIT(0)
224 #define ACCESS_COUNTER_SUBG_HI BIT(0)
227 #define ACCESS_COUNTER_ENG_CLASS GENMASK(11, 9)
234 #define ACCESS_COUNTER_RSVD2 GENMASK(16, 11)
278 #define PFD_RSVD_0 GENMASK(17, 11)
279 #define XE2_PFD_TRVA_FAULT BIT(18)
285 #define PFD_PDATA_HI GENMASK(11, 0)
293 #define PFD_RSVD_1 GENMASK(11, 10)
304 #define PFR_VALID BIT(0)
305 #define PFR_SUCCESS BIT(1)
308 #define PFR_DESC_TYPE GENMASK(11, 10)
313 #define PFR_RSVD_1 BIT(6)
324 #define ACC_TYPE BIT(0)
330 #define ACC_SUBG_HI BIT(0)
333 #define ACC_ENG_CLASS GENMASK(11, 9)
340 #define ACC_RSVD2 GENMASK(16, 11)