1 // SPDX-License-Identifier: MIT
25 	if (drm_WARN_ON(&gt_to_xe(gt)->drm, numregs > XE_MAX_DSS_FUSE_REGS))  in load_dss_mask()
30 		fuse_val[i] = xe_mmio_read32(&gt->mmio, va_arg(argp, struct xe_reg));  in load_dss_mask()
40 	u32 reg_val = xe_mmio_read32(&gt->mmio, XELP_EU_ENABLE);  in load_eu_mask()
47 	 * Pre-Xe_HP platforms inverted the bit meaning (disable instead  in load_eu_mask()
69  * gen_l3_mask_from_pattern - Replicate a bit pattern according to a mask
71  * It is used to compute the L3 bank masks in a generic format on
82  * ----------
96  * ----------
132 	u32 fuse3 = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);  in load_l3_bank_mask()
136 	 * for the media GT's L3 bank registers.  Skip the readout since we  in load_l3_bank_mask()
139 	 * This may get re-described as an official workaround in the future,  in load_l3_bank_mask()
158 		u32 fuse4 = xe_mmio_read32(&gt->mmio, XEHP_FUSE4);  in load_l3_bank_mask()
165 	} else if (xe->info.platform == XE_PVC) {  in load_l3_bank_mask()
176 	} else if (xe->info.platform == XE_DG2) {  in load_l3_bank_mask()
221 	drm_WARN_ON(&xe->drm, num_geometry_regs > 3);  in xe_gt_topology_init()
222 	drm_WARN_ON(&xe->drm, num_compute_regs > 3);  in xe_gt_topology_init()
224 	load_dss_mask(gt, gt->fuse_topo.g_dss_mask,  in xe_gt_topology_init()
229 	load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,  in xe_gt_topology_init()
233 	load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss, &gt->fuse_topo.eu_type);  in xe_gt_topology_init()
234 	load_l3_bank_mask(gt, gt->fuse_topo.l3_bank_mask);  in xe_gt_topology_init()
236 	p = drm_dbg_printer(&gt_to_xe(gt)->drm, DRM_UT_DRIVER, "GT topology");  in xe_gt_topology_init()
257 		   gt->fuse_topo.g_dss_mask);  in xe_gt_topology_dump()
259 		   gt->fuse_topo.c_dss_mask);  in xe_gt_topology_dump()
262 		   gt->fuse_topo.eu_mask_per_dss);  in xe_gt_topology_dump()
264 		   eu_type_to_str(gt->fuse_topo.eu_type));  in xe_gt_topology_dump()
266 	drm_printf(p, "L3 bank mask:        %*pb\n", XE_MAX_L3_BANK_MASK_BITS,  in xe_gt_topology_dump()
267 		   gt->fuse_topo.l3_bank_mask);  in xe_gt_topology_dump()
273  * groupsize and groupnum are non-zero.
287  * xe_gt_topology_has_dss_in_quadrant - check fusing of DSS in GT quadrant
291  * Since Xe_HP platforms can have up to four CCS engines, those engines
293  * are no DSS present in one of the four quadrants of the DSS space, the
304 	bitmap_or(all_dss, gt->fuse_topo.g_dss_mask, gt->fuse_topo.c_dss_mask,  in xe_gt_topology_has_dss_in_quadrant()
317 	return test_bit(dss, gt->fuse_topo.g_dss_mask);  in xe_gt_has_geometry_dss()
322 	return test_bit(dss, gt->fuse_topo.c_dss_mask);  in xe_gt_has_compute_dss()