Lines Matching +full:8 +full:bit
40 ('3' << 8) | \
51 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
52 # define V3D_IDENT1_QUPS_SHIFT 8
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
63 # define V3D_L2CACTL_L2CENA BIT(0)
70 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
71 # define V3D_SLCACTL_UCC_SHIFT 8
78 # define V3D_INT_SPILLUSE BIT(3)
79 # define V3D_INT_OUTOMEM BIT(2)
80 # define V3D_INT_FLDONE BIT(1)
81 # define V3D_INT_FRDONE BIT(0)
86 # define V3D_CTRSTA BIT(15)
87 # define V3D_CTSEMA BIT(12)
88 # define V3D_CTRTSD BIT(8)
89 # define V3D_CTRUN BIT(5)
90 # define V3D_CTSUBS BIT(4)
91 # define V3D_CTERR BIT(3)
92 # define V3D_CTMODE BIT(0)
111 # define V3D_BMOOM BIT(8)
112 # define V3D_RMBUSY BIT(3)
113 # define V3D_RMACTIVE BIT(2)
114 # define V3D_BMBUSY BIT(1)
115 # define V3D_BMACTIVE BIT(0)
135 # define V3D_PCTRE_EN BIT(31)
136 #define V3D_PCTR(x) (0x00680 + ((x) * 8))
137 #define V3D_PCTRS(x) (0x00684 + ((x) * 8))
158 # define PV_CONTROL_CLR_AT_START BIT(14)
159 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
160 # define PV_CONTROL_WAIT_HSTART BIT(12)
168 # define PV_CONTROL_FIFO_CLR BIT(1)
169 # define PV_CONTROL_EN BIT(0)
172 # define PV_VCONTROL_ODD_TIMING BIT(29)
175 # define PV_VCONTROL_ODD_FIRST BIT(5)
176 # define PV_VCONTROL_INTERLACE BIT(4)
177 # define PV_VCONTROL_DSI BIT(3)
178 # define PV_VCONTROL_COMMAND BIT(2)
179 # define PV_VCONTROL_CONTINUOUS BIT(1)
180 # define PV_VCONTROL_VIDEN BIT(0)
213 # define PV_INT_VID_IDLE BIT(9)
214 # define PV_INT_VFP_END BIT(8)
215 # define PV_INT_VFP_START BIT(7)
216 # define PV_INT_VACT_START BIT(6)
217 # define PV_INT_VBP_START BIT(5)
218 # define PV_INT_VSYNC_START BIT(4)
219 # define PV_INT_HFP_START BIT(3)
220 # define PV_INT_HACT_START BIT(2)
221 # define PV_INT_HBP_START BIT(1)
222 # define PV_INT_HSYNC_START BIT(0)
231 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8
234 # define PV_PIPE_INIT_CTRL_PV_INIT_WIDTH_MASK VC4_MASK(11, 8)
236 # define PV_PIPE_INIT_CTRL_PV_INIT_EN BIT(0)
242 # define SCALER_DISPCTRL_ENABLE BIT(31)
256 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
257 # define SCALER5_DISPCTRL_DSPEISLUR(x) BIT(9 + ((x) * 4))
261 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
262 # define SCALER5_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 4))
264 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
265 # define SCALER5_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 4))
267 # define SCALER5_DISPCTRL_DSPEIVST(x) BIT(6 + ((x) * 4))
269 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) /* HVS4 only */
270 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) /* HVS4 only */
271 # define SCALER5_DISPCTRL_SLVEIRQ BIT(5)
272 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
276 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
278 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
288 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
290 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
294 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
298 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
302 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
304 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
306 # define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \
307 8 + ((x) * 8))
310 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
312 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
314 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
318 # define SCALER_DISPSTAT_IRQDMA BIT(4)
320 * corresponding interrupt bit is enabled in DISPCTRL.
322 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
324 # define SCALER_DISPSTAT_IRQSCL BIT(0)
357 # define SCALER_DISPCTRLX_ENABLE BIT(31)
358 # define SCALER_DISPCTRLX_RESET BIT(30)
362 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
366 # define SCALER_DISPCTRLX_ONECTX BIT(28)
368 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
372 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
384 # define SCALER5_DISPCTRLX_ONESHOT BIT(15)
394 # define SCALER_DISPBKGND_AUTOHS BIT(31)
395 # define SCALER5_DISPBKGND_BCK2BCK BIT(31)
396 # define SCALER_DISPBKGND_INTERLACE BIT(30)
397 # define SCALER_DISPBKGND_GAMMA BIT(29)
404 # define SCALER_DISPBKGND_FILL BIT(24)
413 # define SCALER_DISPSTATX_FULL BIT(29)
414 # define SCALER_DISPSTATX_EMPTY BIT(28)
469 # define SCALER_GAMADDR_AUTOINC BIT(31)
473 # define SCALER_GAMADDR_SRAMENB BIT(30)
477 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
487 /* Offsets are 8-bit 2s-complement. */
490 # define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
491 # define SCALER_OLEDOFFS_GREEN_SHIFT 8
526 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
527 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
529 # define SCALER_DISPSLAVE_EOL BIT(26)
531 # define SCALER_DISPSLAVE_EMPTY BIT(25)
533 # define SCALER_DISPSLAVE_VALID BIT(24)
554 # define SCALER6_CONTROL_HVS_EN BIT(31)
556 # define SCALER6_CONTROL_ABORT_ON_EMPTY BIT(16)
568 # define SCALER6_DISPX_CTRL0_ENB BIT(31)
569 # define SCALER6_DISPX_CTRL0_RESET BIT(30)
571 # define SCALER6_DISPX_CTRL0_ONESHOT BIT(15)
579 # define SCALER6_DISPX_CTRL1_BGENB BIT(8)
580 # define SCALER6_DISPX_CTRL1_INTLACE BIT(0)
604 # define SCALER6_DISPX_STATUS_EMPTY BIT(22)
606 # define SCALER6_DISPX_STATUS_OFIELD BIT(15)
743 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
744 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
746 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
748 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
749 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
753 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
754 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
755 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
756 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
760 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
762 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
774 # define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK VC4_MASK(15, 8)
775 # define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT 8
786 VC4_HDMI_MAI_SAMPLE_RATE_44100 = 8,
796 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
801 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
803 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
807 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
811 # define VC4_HDMI_HORZA_VPOS BIT(14)
812 # define VC4_HDMI_HORZA_HPOS BIT(13)
827 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
828 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
829 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
830 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
831 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
832 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
833 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
834 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
835 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
836 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
839 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
840 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
841 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
842 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
843 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
859 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
863 # define VC4_HDMI_CEC_TX_EOM BIT(31)
868 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
869 # define VC4_HDMI_CEC_RX_EOM BIT(29)
870 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
874 /* Sets continuous receive mode. Generates interrupt after each 8
881 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
882 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
884 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
888 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
894 /* Divides off of HSM clock to generate CEC bit clock. */
895 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
899 /* Set these fields to how many bit clock cycles get to that many
917 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
918 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
926 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
927 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
931 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
932 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
933 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
934 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
935 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
938 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
939 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
943 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
945 # define VC4_HDMI_CPU_CEC BIT(6)
946 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
949 # define VC4_HD_CECRXD BIT(9)
951 # define VC4_HD_CECOVR BIT(8)
954 # define VC4_HD_M_SW_RST BIT(2)
955 # define VC4_HD_M_ENABLE BIT(0)
960 # define VC4_HD_MAI_CTL_DLATE BIT(15)
961 # define VC4_HD_MAI_CTL_BUSY BIT(14)
962 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
963 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
964 # define VC4_HD_MAI_CTL_FULL BIT(11)
965 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
966 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
967 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
970 # define VC4_HD_MAI_CTL_PAREN BIT(8)
973 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
974 /* Underflow error status bit, write 1 to clear. */
975 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
976 /* Overflow error status bit, write 1 to clear. */
977 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
978 /* Single-shot reset bit. Read value is undefined. */
979 # define VC4_HD_MAI_CTL_RESET BIT(0)
985 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
986 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
1002 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
1003 # define VC4_HD_MAI_SMP_N_SHIFT 8
1007 # define VC4_HD_VID_CTL_ENABLE BIT(31)
1008 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
1009 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
1010 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
1011 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
1012 # define VC4_HD_VID_CTL_CLRSYNC BIT(24)
1013 # define VC4_HD_VID_CTL_CLRRGB BIT(23)
1014 # define VC4_HD_VID_CTL_BLANKPIX BIT(18)
1015 # define VC4_HD_VID_CTL_BLANK_INSERT_EN BIT(16)
1025 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
1031 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
1032 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
1034 # define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)
1039 # define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
1040 # define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
1048 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
1059 /* 8bpp */
1072 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
1099 /* For YCbCr modes (8-12, and 17) */
1105 #define SCALER_CTL0_END BIT(31)
1106 #define SCALER_CTL0_VALID BIT(30)
1118 #define SCALER_CTL0_ALPHA_MASK BIT(19)
1119 #define SCALER_CTL0_HFLIP BIT(16)
1120 #define SCALER_CTL0_VFLIP BIT(15)
1139 #define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
1141 #define SCALER5_CTL0_RGB_EXPAND BIT(11)
1143 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
1144 #define SCALER_CTL0_SCL1_SHIFT 8
1159 #define SCALER_CTL0_UNITY BIT(4)
1160 #define SCALER5_CTL0_UNITY BIT(15)
1182 #define SCALER5_POS0_VFLIP BIT(31)
1183 #define SCALER5_POS0_HFLIP BIT(15)
1192 #define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
1194 #define SCALER5_CTL2_ALPHA_MIX BIT(28)
1196 #define SCALER5_CTL2_ALPHA_LOC BIT(25)
1201 #define SCALER5_CTL2_GAMMA BIT(16)
1206 #define SCALER6D_CTL2_CSC_ENABLE BIT(19)
1227 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
1228 #define SCALER_POS2_ALPHA_MIX BIT(28)
1242 /* Color Space Conversion words. Some values are S2.8 signed
1246 /* bottom 8 bits of S2.8 contribution of Cr to Blue */
1253 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
1254 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
1265 /* S2.8 contribution of Cb to Green */
1268 /* S2.8 contribution of Cr to Green */
1271 /* S2.8 contribution of Y to all of RGB */
1274 /* top 2 bits of S2.8 contribution of Cr to Blue */
1284 /* S2.8 contribution of Cb to Red */
1287 /* S2.8 contribution of Cr to Red */
1290 /* S2.8 contribution of Cb to Blue */
1300 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1301 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
1302 #define SCALER_TPZ0_SCALE_SHIFT 8
1308 /* Skips interpolating coefficients to 64 phases, so just 8 are used.
1311 #define SCALER_PPF_NOINTERP BIT(31)
1315 #define SCALER_PPF_AGC BIT(30)
1316 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1317 #define SCALER_PPF_SCALE_SHIFT 8
1323 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1342 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1343 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1345 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
1346 #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
1350 #define SCALER6_CTL0_END BIT(31)
1351 #define SCALER6_CTL0_VALID BIT(30)
1353 #define SCALER6_CTL0_RGB_TRANS BIT(23)
1364 #define SCALER6_CTL0_UNITY BIT(15)
1366 #define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)
1371 #define SCALER6_POS0_HFLIP BIT(15)
1375 #define SCALER6_CTL2_ALPHA_PREMULT BIT(29)
1376 #define SCALER6_CTL2_ALPHA_MIX BIT(28)
1377 #define SCALER6_CTL2_BFG BIT(26)
1378 #define SCALER6C_CTL2_CSC_ENABLE BIT(25)
1388 #define SCALER6_PTR0_VFLIP BIT(31)
1391 #define SCALER6_PTR0_UPM_BUFF_SIZE_MASK VC4_MASK(9, 8)