Lines Matching +full:0 +full:x000000c8
36 #define V3D_IDENT0 0x00000
39 ('V' << 0) | \
43 #define V3D_IDENT1 0x00004
55 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
56 # define V3D_IDENT1_REV_SHIFT 0
58 #define V3D_IDENT2 0x00008
59 #define V3D_SCRATCH 0x00010
60 #define V3D_L2CACTL 0x00020
63 # define V3D_L2CACTL_L2CENA BIT(0)
65 #define V3D_SLCACTL 0x00024
72 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
73 # define V3D_SLCACTL_ICC_SHIFT 0
75 #define V3D_INTCTL 0x00030
76 #define V3D_INTENA 0x00034
77 #define V3D_INTDIS 0x00038
81 # define V3D_INT_FRDONE BIT(0)
83 #define V3D_CT0CS 0x00100
84 #define V3D_CT1CS 0x00104
92 # define V3D_CTMODE BIT(0)
94 #define V3D_CT0EA 0x00108
95 #define V3D_CT1EA 0x0010c
97 #define V3D_CT0CA 0x00110
98 #define V3D_CT1CA 0x00114
100 #define V3D_CT00RA0 0x00118
101 #define V3D_CT01RA0 0x0011c
103 #define V3D_CT0LC 0x00120
104 #define V3D_CT1LC 0x00124
106 #define V3D_CT0PC 0x00128
107 #define V3D_CT1PC 0x0012c
110 #define V3D_PCS 0x00130
115 # define V3D_BMACTIVE BIT(0)
117 #define V3D_BFC 0x00134
118 #define V3D_RFC 0x00138
119 #define V3D_BPCA 0x00300
120 #define V3D_BPCS 0x00304
121 #define V3D_BPOA 0x00308
122 #define V3D_BPOS 0x0030c
123 #define V3D_BXCF 0x00310
124 #define V3D_SQRSV0 0x00410
125 #define V3D_SQRSV1 0x00414
126 #define V3D_SQCNTL 0x00418
127 #define V3D_SRQPC 0x00430
128 #define V3D_SRQUA 0x00434
129 #define V3D_SRQUL 0x00438
130 #define V3D_SRQCS 0x0043c
131 #define V3D_VPACNTL 0x00500
132 #define V3D_VPMBASE 0x00504
133 #define V3D_PCTRC 0x00670
134 #define V3D_PCTRE 0x00674
136 #define V3D_PCTR(x) (0x00680 + ((x) * 8))
137 #define V3D_PCTRS(x) (0x00684 + ((x) * 8))
138 #define V3D_DBGE 0x00f00
139 #define V3D_FDBGO 0x00f04
140 #define V3D_FDBGB 0x00f08
141 #define V3D_FDBGR 0x00f0c
142 #define V3D_FDBGS 0x00f10
143 #define V3D_ERRSTAT 0x00f20
145 #define PV_CONTROL 0x00
150 # define PV_CONTROL_FORMAT_24 0
163 # define PV_CONTROL_CLK_SELECT_DSI 0
169 # define PV_CONTROL_EN BIT(0)
171 #define PV_V_CONTROL 0x04
180 # define PV_VCONTROL_VIDEN BIT(0)
182 #define PV_VSYNCD_EVEN 0x08
184 #define PV_HORZA 0x0c
187 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
188 # define PV_HORZA_HSYNC_SHIFT 0
190 #define PV_HORZB 0x10
193 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
194 # define PV_HORZB_HACTIVE_SHIFT 0
196 #define PV_VERTA 0x14
199 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
200 # define PV_VERTA_VSYNC_SHIFT 0
202 #define PV_VERTB 0x18
205 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
206 # define PV_VERTB_VACTIVE_SHIFT 0
208 #define PV_VERTA_EVEN 0x1c
209 #define PV_VERTB_EVEN 0x20
211 #define PV_INTEN 0x24
212 #define PV_INTSTAT 0x28
222 # define PV_INT_HSYNC_START BIT(0)
224 #define PV_STAT 0x2c
226 #define PV_HACT_ACT 0x30
228 #define PV_MUX_CFG 0x34
233 #define PV_PIPE_INIT_CTRL 0x94
236 # define PV_PIPE_INIT_CTRL_PV_INIT_EN BIT(0)
240 #define SCALER_DISPCTRL 0x00000000
252 /* Enables Display 0 short line and underrun contribution to
258 /* Enables Display 0 end-of-line-N contribution to
263 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
278 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
280 #define SCALER_DISPSTAT 0x00000004
283 # define SCALER_DISPSTAT_RESP_OKAY 0
324 # define SCALER_DISPSTAT_IRQSCL BIT(0)
326 #define SCALER_DISPID 0x00000008
327 #define SCALER_DISPECTRL 0x0000000c
331 #define SCALER_DISPPROF 0x00000010
333 #define SCALER_DISPDITHER 0x00000014
337 #define SCALER_DISPEOLN 0x00000018
341 #define SCALER_DISPLIST0 0x00000020
342 #define SCALER_DISPLIST1 0x00000024
343 #define SCALER_DISPLIST2 0x00000028
344 #define SCALER_DISPLSTAT 0x0000002c
349 #define SCALER_DISPLACT0 0x00000030
350 #define SCALER_DISPLACT1 0x00000034
351 #define SCALER_DISPLACT2 0x00000038
356 #define SCALER_DISPCTRL0 0x00000040
376 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
377 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
390 # define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
391 # define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
393 #define SCALER_DISPBKGND0 0x00000044
406 #define SCALER_DISPSTAT0 0x00000048
409 # define SCALER_DISPSTATX_MODE_DISABLED 0
415 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
416 # define SCALER_DISPSTATX_LINE_SHIFT 0
418 #define SCALER_DISPBASE0 0x0000004c
428 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
429 # define SCALER_DISPBASEX_BASE_SHIFT 0
431 #define SCALER_DISPCTRL1 0x00000050
432 #define SCALER_DISPBKGND1 0x00000054
436 #define SCALER_DISPSTAT1 0x00000058
450 #define SCALER_DISPBASE1 0x0000005c
454 #define SCALER_DISPCTRL2 0x00000060
458 #define SCALER_DISPBKGND2 0x00000064
460 #define SCALER_DISPSTAT2 0x00000068
466 #define SCALER_DISPBASE2 0x0000006c
467 #define SCALER_DISPALPHA2 0x00000070
468 #define SCALER_GAMADDR 0x00000078
475 #define SCALER_OLEDOFFS 0x00000080
482 # define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0
492 # define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)
493 # define SCALER_OLEDOFFS_BLUE_SHIFT 0
496 #define SCALER_OLEDCOEF0 0x00000084
501 # define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)
502 # define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0
504 #define SCALER_OLEDCOEF1 0x00000088
509 # define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)
510 # define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0
512 #define SCALER_OLEDCOEF2 0x0000008c
517 # define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)
518 # define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0
523 #define SCALER_DISPSLAVE0 0x000000c0
524 #define SCALER_DISPSLAVE1 0x000000c9
525 #define SCALER_DISPSLAVE2 0x000000d0
534 # define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)
535 # define SCALER_DISPSLAVE_RGB_SHIFT 0
537 #define SCALER_GAMDATA 0x000000e0
538 #define SCALER_DLIST_START 0x00002000
539 #define SCALER_DLIST_SIZE 0x00004000
541 #define SCALER5_DLIST_START 0x00004000
543 #define SCALER6_VERSION 0x00000000
544 # define SCALER6_VERSION_MASK VC4_MASK(7, 0)
545 # define SCALER6_VERSION_C0 0x00000053
546 # define SCALER6_VERSION_D0 0x00000054
547 #define SCALER6_CXM_SIZE 0x00000004
548 #define SCALER6_LBM_SIZE 0x00000008
549 #define SCALER6_UBM_SIZE 0x0000000c
550 #define SCALER6_COBA_SIZE 0x00000010
551 #define SCALER6_COB_SIZE 0x00000014
553 #define SCALER6_CONTROL 0x00000020
560 #define SCALER6_FETCHER_STATUS 0x00000024
561 #define SCALER6_FETCH_STATUS 0x00000028
562 #define SCALER6_HANDLE_ERROR 0x0000002c
564 #define SCALER6_DISP0_CTRL0 0x00000030
573 # define SCALER6_DISPX_CTRL0_LINES_MASK VC4_MASK(12, 0)
575 #define SCALER6_DISP0_CTRL1 0x00000034
580 # define SCALER6_DISPX_CTRL1_INTLACE BIT(0)
582 #define SCALER6_DISP0_BGND 0x00000038
587 #define SCALER6_DISP0_LPTRS 0x0000003c
591 # define SCALER6_DISPX_LPTRS_HEADE_MASK VC4_MASK(11, 0)
593 #define SCALER6_DISP0_COB 0x00000040
598 # define SCALER6_DISPX_COB_BASE_MASK VC4_MASK(15, 0)
600 #define SCALER6_DISP0_STATUS 0x00000044
608 # define SCALER6_DISPX_STATUS_MODE_DISABLED 0
612 # define SCALER6_DISPX_STATUS_YLINE_MASK VC4_MASK(12, 0)
614 #define SCALER6_DISP0_DL 0x00000048
619 # define SCALER6_DISPX_DL_LACT_MASK VC4_MASK(11, 0)
621 #define SCALER6_DISP0_RUN 0x0000004c
622 #define SCALER6_DISP1_CTRL0 0x00000050
623 #define SCALER6_DISP1_CTRL1 0x00000054
624 #define SCALER6_DISP1_BGND 0x00000058
625 #define SCALER6_DISP1_LPTRS 0x0000005c
626 #define SCALER6_DISP1_COB 0x00000060
627 #define SCALER6_DISP1_STATUS 0x00000064
628 #define SCALER6_DISP1_DL 0x00000068
629 #define SCALER6_DISP1_RUN 0x0000006c
630 #define SCALER6_DISP2_CTRL0 0x00000070
631 #define SCALER6_DISP2_CTRL1 0x00000074
632 #define SCALER6_DISP2_BGND 0x00000078
633 #define SCALER6_DISP2_LPTRS 0x0000007c
634 #define SCALER6_DISP2_COB 0x00000080
635 #define SCALER6_DISP2_STATUS 0x00000084
636 #define SCALER6_DISP2_DL 0x00000088
637 #define SCALER6_DISP2_RUN 0x0000008c
638 #define SCALER6_EOLN 0x00000090
639 #define SCALER6_DL_STATUS 0x00000094
640 #define SCALER6_BFG_MISC 0x0000009c
641 #define SCALER6_QOS0 0x000000a0
642 #define SCALER6_PROF0 0x000000a4
643 #define SCALER6_QOS1 0x000000a8
644 #define SCALER6_PROF1 0x000000ac
645 #define SCALER6_QOS2 0x000000b0
646 #define SCALER6_PROF2 0x000000b4
647 #define SCALER6_PRI_MAP0 0x000000b8
648 #define SCALER6_PRI_MAP1 0x000000bc
649 #define SCALER6_HISTCTRL 0x000000c0
650 #define SCALER6_HISTBIN0 0x000000c4
651 #define SCALER6_HISTBIN1 0x000000c8
652 #define SCALER6_HISTBIN2 0x000000cc
653 #define SCALER6_HISTBIN3 0x000000d0
654 #define SCALER6_HISTBIN4 0x000000d4
655 #define SCALER6_HISTBIN5 0x000000d8
656 #define SCALER6_HISTBIN6 0x000000dc
657 #define SCALER6_HISTBIN7 0x000000e0
658 #define SCALER6_HDR_CFG_REMAP 0x000000f4
659 #define SCALER6_COL_SPACE 0x000000f8
660 #define SCALER6_HVS_ID 0x000000fc
661 #define SCALER6_CFC1 0x00000100
662 #define SCALER6_DISP_UPM_ISO0 0x00000200
663 #define SCALER6_DISP_UPM_ISO1 0x00000204
664 #define SCALER6_DISP_UPM_ISO2 0x00000208
665 #define SCALER6_DISP_LBM_ISO0 0x0000020c
666 #define SCALER6_DISP_LBM_ISO1 0x00000210
667 #define SCALER6_DISP_LBM_ISO2 0x00000214
668 #define SCALER6_DISP_COB_ISO0 0x00000218
669 #define SCALER6_DISP_COB_ISO1 0x0000021c
670 #define SCALER6_DISP_COB_ISO2 0x00000220
671 #define SCALER6_BAD_COB 0x00000224
672 #define SCALER6_BAD_LBM 0x00000228
673 #define SCALER6_BAD_UPM 0x0000022c
674 #define SCALER6_BAD_AXI 0x00000230
676 #define SCALER6D_VERSION 0x00000000
677 #define SCALER6D_CXM_SIZE 0x00000004
678 #define SCALER6D_LBM_SIZE 0x00000008
679 #define SCALER6D_UBM_SIZE 0x0000000c
680 #define SCALER6D_COBA_SIZE 0x00000010
681 #define SCALER6D_COB_SIZE 0x00000014
682 #define SCALER6D_CONTROL 0x00000020
683 #define SCALER6D_FETCHER_STATUS 0x00000024
684 #define SCALER6D_FETCH_STATUS 0x00000028
685 #define SCALER6D_HANDLE_ERROR 0x0000002c
686 #define SCALER6D_EOLN 0x00000030
687 #define SCALER6D_DL_STATUS 0x00000034
688 #define SCALER6D_PRI_MAP0 0x00000038
689 #define SCALER6D_PRI_MAP1 0x0000003c
690 #define SCALER6D_HISTCTRL 0x000000d0
691 #define SCALER6D_HISTBIN0 0x000000d4
692 #define SCALER6D_HISTBIN1 0x000000d8
693 #define SCALER6D_HISTBIN2 0x000000dc
694 #define SCALER6D_HISTBIN3 0x000000e0
695 #define SCALER6D_HISTBIN4 0x000000e4
696 #define SCALER6D_HISTBIN5 0x000000e8
697 #define SCALER6D_HISTBIN6 0x000000ec
698 #define SCALER6D_HISTBIN7 0x000000f0
699 #define SCALER6D_HVS_ID 0x000000fc
701 #define SCALER6D_DISP0_CTRL0 0x00000100
702 #define SCALER6D_DISP0_CTRL1 0x00000104
703 #define SCALER6D_DISP0_BGND 0x00000108
704 #define SCALER6D_DISP0_LPTRS 0x00000110
705 #define SCALER6D_DISP0_COB 0x00000114
706 #define SCALER6D_DISP0_STATUS 0x00000118
707 #define SCALER6D_DISP0_CTRL0 0x00000100
708 #define SCALER6D_DISP0_CTRL1 0x00000104
709 #define SCALER6D_DISP0_BGND0 0x00000108
710 #define SCALER6D_DISP0_BGND1 0x0000010c
711 #define SCALER6D_DISP0_LPTRS 0x00000110
712 #define SCALER6D_DISP0_COB 0x00000114
713 #define SCALER6D_DISP0_STATUS 0x00000118
714 #define SCALER6D_DISP0_DL 0x0000011c
715 #define SCALER6D_DISP0_RUN 0x00000120
716 #define SCALER6D_QOS0 0x00000124
717 #define SCALER6D_PROF0 0x00000128
718 #define SCALER6D_DISP1_CTRL0 0x00000140
719 #define SCALER6D_DISP1_CTRL1 0x00000144
720 #define SCALER6D_DISP1_BGND0 0x00000148
721 #define SCALER6D_DISP1_BGND1 0x0000014c
722 #define SCALER6D_DISP1_LPTRS 0x00000150
723 #define SCALER6D_DISP1_COB 0x00000154
724 #define SCALER6D_DISP1_STATUS 0x00000158
725 #define SCALER6D_DISP1_DL 0x0000015c
726 #define SCALER6D_DISP1_RUN 0x00000160
727 #define SCALER6D_QOS1 0x00000164
728 #define SCALER6D_PROF1 0x00000168
729 #define SCALER6D_DISP2_CTRL0 0x00000180
730 #define SCALER6D_DISP2_CTRL1 0x00000184
731 #define SCALER6D_DISP2_BGND0 0x00000188
732 #define SCALER6D_DISP2_BGND1 0x0000018c
733 #define SCALER6D_DISP2_LPTRS 0x00000190
734 #define SCALER6D_DISP2_COB 0x00000194
735 #define SCALER6D_DISP2_STATUS 0x00000198
736 #define SCALER6D_DISP2_DL 0x0000019c
737 #define SCALER6D_DISP2_RUN 0x000001a0
738 #define SCALER6D_QOS2 0x000001a4
739 #define SCALER6D_PROF2 0x000001a8
744 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
746 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
750 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)
751 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0
763 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)
764 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0
778 VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED = 0,
808 # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)
809 # define VC4_HDMI_CRP_CFG_N_SHIFT 0
814 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
815 # define VC4_HDMI_HORZA_HAP_SHIFT 0
824 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
825 # define VC4_HDMI_HORZB_HFP_SHIFT 0
836 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
837 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
843 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
852 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
853 # define VC4_HDMI_VERTA_VAL_SHIFT 0
859 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
860 # define VC4_HDMI_VERTB_VBP_SHIFT 0
896 # define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
897 # define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
910 # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
911 # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
919 # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
920 # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
928 # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
929 # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
940 # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
941 # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
946 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
950 /* Debug: Override CEC output to 0. */
955 # define VC4_HD_M_ENABLE BIT(0)
979 # define VC4_HD_MAI_CTL_RESET BIT(0)
987 # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
988 # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
996 # define VC6_D_HD_MAI_THR_DREQLOW_MASK VC4_MASK(6, 0)
997 # define VC6_D_HD_MAI_THR_DREQLOW_SHIFT 0
1004 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)
1005 # define VC4_HD_MAI_SMP_M_SHIFT 0
1019 # define VC4_HD_CSC_CTL_ORDER_RGB 0
1028 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
1032 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
1041 # define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
1060 HVS_PIXEL_FORMAT_RGB332 = 0,
1088 #define HVS_PIXEL_ORDER_RGBA 0
1094 #define HVS_PIXEL_ORDER_XBRG 0
1100 #define HVS_PIXEL_ORDER_XYCBCR 0
1113 #define SCALER_CTL0_TILING_LINEAR 0
1124 #define SCALER_CTL0_KEY_DISABLED 0
1134 #define SCALER_CTL0_RGBA_EXPAND_ZERO 0
1149 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0
1162 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
1163 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
1165 #define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
1173 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
1174 #define SCALER_POS0_START_X_SHIFT 0
1179 #define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
1180 #define SCALER5_POS0_START_X_SHIFT 0
1187 #define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
1212 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
1213 #define SCALER_POS1_SCL_WIDTH_SHIFT 0
1218 #define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
1219 #define SCALER5_POS1_SCL_WIDTH_SHIFT 0
1223 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0
1233 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
1234 #define SCALER_POS2_WIDTH_SHIFT 0
1239 #define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
1240 #define SCALER5_POS2_WIDTH_SHIFT 0
1243 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
1244 * 0x2: 2, 0x3: -1}
1256 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
1257 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
1258 #define SCALER_CSC0_ITR_R_601_5 0x00f00000
1259 #define SCALER_CSC0_ITR_R_709_3 0x00f00000
1260 #define SCALER_CSC0_ITR_R_2020 0x00f00000
1261 #define SCALER_CSC0_JPEG_JFIF 0x00000000
1262 #define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
1263 #define SCALER_CSC0_ITR_R_2020_FR 0x00000000
1275 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
1276 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
1277 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8
1278 #define SCALER_CSC1_ITR_R_709_3 0xf27784a8
1279 #define SCALER_CSC1_ITR_R_2020 0xf43594a8
1280 #define SCALER_CSC1_JPEG_JFIF 0xea349400
1281 #define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
1282 #define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
1293 #define SCALER_CSC2_ITR_R_601_5 0x00066604
1294 #define SCALER_CSC2_ITR_R_709_3 0x00072e1d
1295 #define SCALER_CSC2_ITR_R_2020 0x0006b624
1296 #define SCALER_CSC2_JPEG_JFIF 0x00059dc6
1297 #define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
1298 #define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
1303 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
1304 #define SCALER_TPZ0_IPHASE_SHIFT 0
1305 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
1306 #define SCALER_TPZ1_RECIP_SHIFT 0
1318 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
1319 #define SCALER_PPF_IPHASE_SHIFT 0
1321 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
1322 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
1326 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
1327 #define SCALER_SRC_PITCH_SHIFT 0
1332 #define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
1333 #define SCALER_TILE_HEIGHT_SHIFT 0
1347 #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
1348 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
1355 #define SCALER6_CTL0_ADDR_MODE_LINEAR 0
1362 #define SCALER6_CTL0_ALPHA_MASK_NONE 0
1368 #define SCALER6_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
1372 #define SCALER6_POS0_START_X_MASK VC4_MASK(12, 0)
1383 #define SCALER6_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
1386 #define SCALER6_POS2_SRC_WIDTH_MASK VC4_MASK(12, 0)
1395 #define SCALER6_PTR0_UPM_BUFF_SIZE_2_LINES 0
1396 #define SCALER6_PTR0_UPPER_ADDR_MASK VC4_MASK(7, 0)
1400 #define SCALER6_PTR2_ALPHA_BPP_8BPP 0
1403 #define SCALER6_PTR2_ALPHA_ORDER_LSB_TO_MSB 0
1406 #define SCALER6_PTR2_PITCH_MASK VC4_MASK(16, 0)