Lines Matching +full:bcm2711 +full:- +full:hdmi0
1 // SPDX-License-Identifier: GPL-2.0-only
49 struct drm_device *dev = state->dev; in vc4_get_ctm_state()
54 ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); in vc4_get_ctm_state()
70 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_ctm_duplicate_state()
74 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_ctm_duplicate_state()
76 return &state->base; in vc4_ctm_duplicate_state()
96 drm_atomic_private_obj_fini(&vc4->ctm_manager); in vc4_ctm_obj_fini()
103 drm_modeset_lock_init(&vc4->ctm_state_lock); in vc4_ctm_obj_init()
107 return -ENOMEM; in vc4_ctm_obj_init()
109 drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base, in vc4_ctm_obj_init()
112 return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL); in vc4_ctm_obj_init()
137 struct vc4_hvs *hvs = vc4->hvs; in vc4_ctm_commit()
138 struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); in vc4_ctm_commit()
139 struct drm_color_ctm *ctm = ctm_state->ctm; in vc4_ctm_commit()
141 WARN_ON_ONCE(vc4->gen > VC4_GEN_5); in vc4_ctm_commit()
143 if (ctm_state->fifo) { in vc4_ctm_commit()
145 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
147 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
149 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
152 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
154 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
156 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
159 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
161 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
163 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
168 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
174 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_new_global_state()
177 priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_new_global_state()
179 return ERR_PTR(-EINVAL); in vc4_hvs_get_new_global_state()
187 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_old_global_state()
190 priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_old_global_state()
192 return ERR_PTR(-EINVAL); in vc4_hvs_get_old_global_state()
200 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_global_state()
203 priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_global_state()
213 struct vc4_hvs *hvs = vc4->hvs; in vc4_hvs_pv_muxing_commit()
218 WARN_ON_ONCE(vc4->gen != VC4_GEN_4); in vc4_hvs_pv_muxing_commit()
226 if (!crtc_state->active) in vc4_hvs_pv_muxing_commit()
229 if (vc4_state->assigned_channel != 2) in vc4_hvs_pv_muxing_commit()
239 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 in vc4_hvs_pv_muxing_commit()
242 if (vc4_crtc->feeds_txp) in vc4_hvs_pv_muxing_commit()
256 struct vc4_hvs *hvs = vc4->hvs; in vc5_hvs_pv_muxing_commit()
263 WARN_ON_ONCE(vc4->gen != VC4_GEN_5); in vc5_hvs_pv_muxing_commit()
268 unsigned int channel = vc4_state->assigned_channel; in vc5_hvs_pv_muxing_commit()
270 if (!vc4_state->update_muxing) in vc5_hvs_pv_muxing_commit()
273 switch (vc4_crtc->data->hvs_output) { in vc5_hvs_pv_muxing_commit()
275 drm_WARN_ON(&vc4->base, in vc5_hvs_pv_muxing_commit()
332 struct vc4_hvs *hvs = vc4->hvs; in vc6_hvs_pv_muxing_commit()
337 WARN_ON_ONCE(vc4->gen != VC4_GEN_6_C && vc4->gen != VC4_GEN_6_D); in vc6_hvs_pv_muxing_commit()
346 if (!vc4_state->update_muxing) in vc6_hvs_pv_muxing_commit()
349 if (vc4_state->assigned_channel != 1) in vc6_hvs_pv_muxing_commit()
354 switch (vc4_encoder->type) { in vc6_hvs_pv_muxing_commit()
364 drm_err(&vc4->base, "Unhandled encoder type for PV muxing %d", in vc6_hvs_pv_muxing_commit()
365 vc4_encoder->type); in vc6_hvs_pv_muxing_commit()
379 struct drm_device *dev = state->dev; in vc4_atomic_commit_tail()
381 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_commit_tail()
394 if (vc4->gen < VC4_GEN_6_C) { in vc4_atomic_commit_tail()
402 if (!new_crtc_state->commit) in vc4_atomic_commit_tail()
406 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel); in vc4_atomic_commit_tail()
414 if (!old_hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_tail()
417 commit = old_hvs_state->fifo_state[channel].pending_commit; in vc4_atomic_commit_tail()
426 old_hvs_state->fifo_state[channel].pending_commit = NULL; in vc4_atomic_commit_tail()
429 if (vc4->gen == VC4_GEN_5) { in vc4_atomic_commit_tail()
430 unsigned long state_rate = max(old_hvs_state->core_clock_rate, in vc4_atomic_commit_tail()
431 new_hvs_state->core_clock_rate); in vc4_atomic_commit_tail()
433 500000000, hvs->max_core_rate); in vc4_atomic_commit_tail()
441 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
442 WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate)); in vc4_atomic_commit_tail()
447 if (vc4->gen <= VC4_GEN_5) in vc4_atomic_commit_tail()
450 switch (vc4->gen) { in vc4_atomic_commit_tail()
465 drm_err(dev, "Unknown VC4 generation: %d", vc4->gen); in vc4_atomic_commit_tail()
482 if (vc4->gen == VC4_GEN_5) { in vc4_atomic_commit_tail()
484 hvs->max_core_rate, in vc4_atomic_commit_tail()
485 new_hvs_state->core_clock_rate); in vc4_atomic_commit_tail()
493 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
494 WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate)); in vc4_atomic_commit_tail()
497 clk_get_rate(hvs->core_clk)); in vc4_atomic_commit_tail()
516 vc4_crtc_state->assigned_channel; in vc4_atomic_commit_setup()
521 if (!hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_setup()
524 hvs_state->fifo_state[channel].pending_commit = in vc4_atomic_commit_setup()
525 drm_crtc_commit_get(crtc_state->commit); in vc4_atomic_commit_setup()
538 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_fb_create()
539 return ERR_PTR(-ENODEV); in vc4_fb_create()
544 if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { in vc4_fb_create()
549 mode_cmd->handles[0]); in vc4_fb_create()
552 mode_cmd->handles[0]); in vc4_fb_create()
553 return ERR_PTR(-ENOENT); in vc4_fb_create()
559 if (bo->t_format) { in vc4_fb_create()
590 if (!new_crtc_state->ctm && old_crtc_state->ctm) { in vc4_ctm_atomic_check()
591 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
594 ctm_state->fifo = 0; in vc4_ctm_atomic_check()
599 if (new_crtc_state->ctm == old_crtc_state->ctm) in vc4_ctm_atomic_check()
603 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
609 if (new_crtc_state->ctm) { in vc4_ctm_atomic_check()
613 /* fifo is 1-based since 0 disables CTM. */ in vc4_ctm_atomic_check()
614 int fifo = vc4_crtc_state->assigned_channel + 1; in vc4_ctm_atomic_check()
619 if (ctm_state->fifo && ctm_state->fifo != fifo) { in vc4_ctm_atomic_check()
621 return -EINVAL; in vc4_ctm_atomic_check()
628 ctm = new_crtc_state->ctm->data; in vc4_ctm_atomic_check()
629 for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { in vc4_ctm_atomic_check()
630 u64 val = ctm->matrix[i]; in vc4_ctm_atomic_check()
634 return -EINVAL; in vc4_ctm_atomic_check()
637 ctm_state->fifo = fifo; in vc4_ctm_atomic_check()
638 ctm_state->ctm = ctm; in vc4_ctm_atomic_check()
648 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_load_tracker_atomic_check()
655 &vc4->load_tracker); in vc4_load_tracker_atomic_check()
664 if (old_plane_state->fb && old_plane_state->crtc) { in vc4_load_tracker_atomic_check()
666 load_state->membus_load -= vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
667 load_state->hvs_load -= vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
670 if (new_plane_state->fb && new_plane_state->crtc) { in vc4_load_tracker_atomic_check()
672 load_state->membus_load += vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
673 load_state->hvs_load += vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
678 if (!vc4->load_tracker_enabled) in vc4_load_tracker_atomic_check()
684 if (load_state->membus_load > SZ_1G + SZ_512M) in vc4_load_tracker_atomic_check()
685 return -ENOSPC; in vc4_load_tracker_atomic_check()
690 if (load_state->hvs_load > 240000000ULL) in vc4_load_tracker_atomic_check()
691 return -ENOSPC; in vc4_load_tracker_atomic_check()
701 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_load_tracker_duplicate_state()
705 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_load_tracker_duplicate_state()
707 return &state->base; in vc4_load_tracker_duplicate_state()
728 drm_atomic_private_obj_fini(&vc4->load_tracker); in vc4_load_tracker_obj_fini()
737 return -ENOMEM; in vc4_load_tracker_obj_init()
739 drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker, in vc4_load_tracker_obj_init()
740 &load_state->base, in vc4_load_tracker_obj_init()
743 return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); in vc4_load_tracker_obj_init()
749 struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state); in vc4_hvs_channels_duplicate_state()
757 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_hvs_channels_duplicate_state()
760 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use; in vc4_hvs_channels_duplicate_state()
761 state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load; in vc4_hvs_channels_duplicate_state()
764 state->core_clock_rate = old_state->core_clock_rate; in vc4_hvs_channels_duplicate_state()
766 return &state->base; in vc4_hvs_channels_duplicate_state()
776 if (!hvs_state->fifo_state[i].pending_commit) in vc4_hvs_channels_destroy_state()
779 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit); in vc4_hvs_channels_destroy_state()
792 drm_printf(p, "\tCore Clock Rate: %lu\n", hvs_state->core_clock_rate); in vc4_hvs_channels_print_state()
796 drm_printf(p, "\t\tin use=%d\n", hvs_state->fifo_state[i].in_use); in vc4_hvs_channels_print_state()
797 drm_printf(p, "\t\tload=%lu\n", hvs_state->fifo_state[i].fifo_load); in vc4_hvs_channels_print_state()
811 drm_atomic_private_obj_fini(&vc4->hvs_channels); in vc4_hvs_channels_obj_fini()
820 return -ENOMEM; in vc4_hvs_channels_obj_init()
822 drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels, in vc4_hvs_channels_obj_init()
823 &state->base, in vc4_hvs_channels_obj_init()
826 return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL); in vc4_hvs_channels_obj_init()
840 return data_a->hvs_output - data_b->hvs_output; in cmp_vc4_crtc_hvs_output()
844 * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
852 * - When running in a dual-display setup (so with two CRTCs involved),
859 * - To fix the above, we can't use drm_atomic_get_crtc_state on all
865 * doing a modetest -v first on HDMI1 and then on HDMI0.
867 * - Since we need the pixelvalve to be disabled and enabled back when
887 for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++) in vc4_pv_muxing_atomic_check()
888 if (!hvs_new_state->fifo_state[i].in_use) in vc4_pv_muxing_atomic_check()
912 sorted_crtcs = kmalloc_array(dev->num_crtcs, sizeof(*sorted_crtcs), GFP_KERNEL); in vc4_pv_muxing_atomic_check()
914 return -ENOMEM; in vc4_pv_muxing_atomic_check()
922 for (i = 0; i < dev->num_crtcs; i++) { in vc4_pv_muxing_atomic_check()
944 drm_dbg(dev, "%s: Trying to find a channel.\n", crtc->name); in vc4_pv_muxing_atomic_check()
947 if (old_crtc_state->enable == new_crtc_state->enable) { in vc4_pv_muxing_atomic_check()
948 if (new_crtc_state->enable) in vc4_pv_muxing_atomic_check()
950 crtc->name, new_vc4_crtc_state->assigned_channel); in vc4_pv_muxing_atomic_check()
952 drm_dbg(dev, "%s: Disabled, ignoring.\n", crtc->name); in vc4_pv_muxing_atomic_check()
958 new_vc4_crtc_state->update_muxing = true; in vc4_pv_muxing_atomic_check()
961 if (!new_crtc_state->enable) { in vc4_pv_muxing_atomic_check()
962 channel = old_vc4_crtc_state->assigned_channel; in vc4_pv_muxing_atomic_check()
965 crtc->name, channel); in vc4_pv_muxing_atomic_check()
967 hvs_new_state->fifo_state[channel].in_use = false; in vc4_pv_muxing_atomic_check()
968 new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; in vc4_pv_muxing_atomic_check()
972 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels; in vc4_pv_muxing_atomic_check()
974 ret = -EINVAL; in vc4_pv_muxing_atomic_check()
978 channel = ffs(matching_channels) - 1; in vc4_pv_muxing_atomic_check()
980 drm_dbg(dev, "Assigned HVS channel %d to CRTC %s\n", channel, crtc->name); in vc4_pv_muxing_atomic_check()
981 new_vc4_crtc_state->assigned_channel = channel; in vc4_pv_muxing_atomic_check()
983 hvs_new_state->fifo_state[channel].in_use = true; in vc4_pv_muxing_atomic_check()
997 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_core_clock_atomic_check()
1009 &vc4->load_tracker); in vc4_core_clock_atomic_check()
1023 if (old_crtc_state->active) { in vc4_core_clock_atomic_check()
1026 unsigned int channel = old_vc4_state->assigned_channel; in vc4_core_clock_atomic_check()
1028 hvs_new_state->fifo_state[channel].fifo_load = 0; in vc4_core_clock_atomic_check()
1031 if (new_crtc_state->active) { in vc4_core_clock_atomic_check()
1034 unsigned int channel = new_vc4_state->assigned_channel; in vc4_core_clock_atomic_check()
1036 hvs_new_state->fifo_state[channel].fifo_load = in vc4_core_clock_atomic_check()
1037 new_vc4_state->hvs_load; in vc4_core_clock_atomic_check()
1044 if (!hvs_new_state->fifo_state[i].in_use) in vc4_core_clock_atomic_check()
1049 hvs_new_state->fifo_state[i].fifo_load, in vc4_core_clock_atomic_check()
1053 pixel_rate = load_state->hvs_load; in vc4_core_clock_atomic_check()
1060 hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate); in vc4_core_clock_atomic_check()
1114 * the BCM2711, but the load tracker computations are used for in vc4_kms_load()
1117 if (vc4->gen == VC4_GEN_4) { in vc4_kms_load()
1121 vc4->load_tracker_enabled = true; in vc4_kms_load()
1125 dev->vblank_disable_immediate = true; in vc4_kms_load()
1127 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); in vc4_kms_load()
1129 dev_err(dev->dev, "failed to initialize vblank\n"); in vc4_kms_load()
1133 if (vc4->gen >= VC4_GEN_6_C) { in vc4_kms_load()
1134 dev->mode_config.max_width = 8192; in vc4_kms_load()
1135 dev->mode_config.max_height = 8192; in vc4_kms_load()
1136 } else if (vc4->gen >= VC4_GEN_5) { in vc4_kms_load()
1137 dev->mode_config.max_width = 7680; in vc4_kms_load()
1138 dev->mode_config.max_height = 7680; in vc4_kms_load()
1140 dev->mode_config.max_width = 2048; in vc4_kms_load()
1141 dev->mode_config.max_height = 2048; in vc4_kms_load()
1144 dev->mode_config.funcs = (vc4->gen > VC4_GEN_4) ? &vc5_mode_funcs : &vc4_mode_funcs; in vc4_kms_load()
1145 dev->mode_config.helper_private = &vc4_mode_config_helpers; in vc4_kms_load()
1146 dev->mode_config.preferred_depth = 24; in vc4_kms_load()
1147 dev->mode_config.async_page_flip = true; in vc4_kms_load()
1148 dev->mode_config.normalize_zpos = true; in vc4_kms_load()