137 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_ctm_commit()  local
213 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_hvs_pv_muxing_commit()  local
256 	struct vc4_hvs *hvs = vc4->hvs;  in vc5_hvs_pv_muxing_commit()  local
332 	struct vc4_hvs *hvs = vc4->hvs;  in vc6_hvs_pv_muxing_commit()  local
381 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_atomic_commit_tail()  local
406 			vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel);  in vc4_atomic_commit_tail()
433 						  500000000, hvs->max_core_rate);  in vc4_atomic_commit_tail()
441 		WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));  in vc4_atomic_commit_tail()
442 		WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate));  in vc4_atomic_commit_tail()
484 						hvs->max_core_rate,  in vc4_atomic_commit_tail()
490 		 * Request a clock rate based on the current HVS  in vc4_atomic_commit_tail()
493 		WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));  in vc4_atomic_commit_tail()
494 		WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate));  in vc4_atomic_commit_tail()
497 			clk_get_rate(hvs->core_clk));  in vc4_atomic_commit_tail()
687 	/* HVS clock is supposed to run @ 250Mhz, let's take a margin and  in vc4_load_tracker_atomic_check()
791 	drm_printf(p, "HVS State\n");  in vc4_hvs_channels_print_state()
844  * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
896 	 * or 3 HVS FIFOs, and we need to set the muxing between FIFOs and  in vc4_pv_muxing_atomic_check()
897 	 * outputs in the HVS accordingly.  in vc4_pv_muxing_atomic_check()
980 		drm_dbg(dev, "Assigned HVS channel %d to CRTC %s\n", channel, crtc->name);  in vc4_pv_muxing_atomic_check()