220 			 readl((u32 __iomem *)hvs->dlist + i + 1),  in vc4_hvs_dump_state()
342 	for (i = 1; i <= VC4_NUM_UPM_HANDLES; i++) {  in vc6_hvs_debugfs_upm_allocs()
368 				c9, c10, c11, c12, c13, c14, c15)	\  argument
373 	 VC4_PPF_FILTER_WORD(c12, c13, c14),				\
377 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
379 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
411 			writel(kernel[VC4_KERNEL_DWORDS - i - 1],  in vc4_hvs_upload_linear_kernel()
497 		case 1:  in vc4_hvs_get_fifo_frame_count()
513 		case 1:  in vc4_hvs_get_fifo_frame_count()
556 		case 1:  in vc4_hvs_get_fifo_from_output()
557 			return 1;  in vc4_hvs_get_fifo_from_output()
604 		case 1:  in vc4_hvs_get_fifo_from_output()
607 			return 1;  in vc4_hvs_get_fifo_from_output()
708 		  VC4_SET_FIELD(mode->hdisplay - 1,  in vc6_hvs_init_channel()
711 		  VC4_SET_FIELD(mode->vdisplay - 1,  in vc6_hvs_init_channel()
802 	 * 1:1 with connectors.)  in vc4_hvs_atomic_check()
804 	if (hweight32(crtc_state->connector_mask) > 1)  in vc4_hvs_atomic_check()
1154 				   SCALER_DISPSTAT_IRQMASK(1) |  in vc4_hvs_irq_handler()
1334 		    SCALER_DISPCTRL_DISPEIRQ(1) |  in vc4_hvs_hw_init()
1342 			      SCALER_DISPCTRL_DSPEIEOF(1) |  in vc4_hvs_hw_init()
1345 			      SCALER_DISPCTRL_DSPEIEOLN(1) |  in vc4_hvs_hw_init()
1348 			      SCALER_DISPCTRL_DSPEISLUR(1) |  in vc4_hvs_hw_init()
1355 			      SCALER5_DISPCTRL_DSPEIEOF(1) |  in vc4_hvs_hw_init()
1358 			      SCALER5_DISPCTRL_DSPEIEOLN(1) |  in vc4_hvs_hw_init()
1361 			      SCALER5_DISPCTRL_DSPEISLUR(1) |  in vc4_hvs_hw_init()
1368 	 * VC5 panics when less than 1 line in the FIFO.  in vc4_hvs_hw_init()
1379 	 * VC5 panics when less than 1 line in the FIFO.  in vc4_hvs_hw_init()
1421 /* 4 S2.22 multiplication factors, and 1 S9.15 addititive element for each of 3
1496 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]);  in vc6_hvs_hw_init()
1501 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]);  in vc6_hvs_hw_init()
1502 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C11(i), coeffs->csc[1][1]);  in vc6_hvs_hw_init()
1503 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C12(i), coeffs->csc[1][2]);  in vc6_hvs_hw_init()
1504 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C13(i), coeffs->csc[1][3]);  in vc6_hvs_hw_init()
1505 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C14(i), coeffs->csc[1][4]);  in vc6_hvs_hw_init()
1508 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C21(i), coeffs->csc[2][1]);  in vc6_hvs_hw_init()
1549 		 * Assign 3 lines to channels 1 & 2, and just over 4 lines to  in vc4_hvs_cob_init()
1557 		reg |= (top - 1) << 16;  in vc4_hvs_cob_init()
1561 		reg |= (top - 1) << 16;  in vc4_hvs_cob_init()
1565 		reg |= (top - 1) << 16;  in vc4_hvs_cob_init()
1575 		 * Assign 3 lines of 4096 to channels 1 & 2, and just over 4  in vc4_hvs_cob_init()
1611 		HVS_WRITE(SCALER6_DISPX_COB(1),  in vc4_hvs_cob_init()