Lines Matching +full:12 +full:bit +full:- +full:clk +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0-only
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
88 # define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
89 # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
90 # define DSI_TXPKT1C_CMD_TE_EN BIT(1)
91 # define DSI_TXPKT1C_CMD_EN BIT(0)
105 # define DSI_RXPKT1H_CRC_ERR BIT(31)
106 # define DSI_RXPKT1H_DET_ERR BIT(30)
107 # define DSI_RXPKT1H_ECC_ERR BIT(29)
108 # define DSI_RXPKT1H_COR_ERR BIT(28)
109 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
110 # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
124 # define DSI_RXPKT1H_DET_ERR BIT(30)
125 # define DSI_RXPKT1H_ECC_ERR BIT(29)
126 # define DSI_RXPKT1H_COR_ERR BIT(28)
127 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
139 # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
146 * of going to LP-STOP.
148 # define DSI_DISP_HACTIVE_NULL BIT(10)
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150 # define DSI_DISP_VBLP_CTRL BIT(9)
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152 # define DSI_DISP_HFP_CTRL BIT(8)
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154 # define DSI_DISP_HBP_CTRL BIT(7)
158 # define DSI_DISP0_ST_END BIT(4)
166 # define DSI_DISP0_COMMAND_MODE BIT(1)
167 # define DSI_DISP0_ENABLE BIT(0)
180 # define DSI_DISP1_ENABLE BIT(0)
186 # define DSI0_INT_FIFO_ERR BIT(25)
191 # define DSI0_INT_PHY_DIR_RTF BIT(22)
192 # define DSI0_INT_PHY_D1_ULPS BIT(21)
193 # define DSI0_INT_PHY_D1_STOP BIT(20)
194 # define DSI0_INT_PHY_RXLPDT BIT(19)
195 # define DSI0_INT_PHY_RXTRIG BIT(18)
196 # define DSI0_INT_PHY_D0_ULPS BIT(17)
197 # define DSI0_INT_PHY_D0_LPDT BIT(16)
198 # define DSI0_INT_PHY_D0_FTR BIT(15)
199 # define DSI0_INT_PHY_D0_STOP BIT(14)
201 # define DSI0_INT_PHY_CLK_ULPS BIT(13)
202 # define DSI0_INT_PHY_CLK_HS BIT(12)
203 # define DSI0_INT_PHY_CLK_FTR BIT(11)
205 # define DSI0_INT_PR_TO BIT(10)
206 # define DSI0_INT_TA_TO BIT(9)
207 # define DSI0_INT_LPRX_TO BIT(8)
208 # define DSI0_INT_HSTX_TO BIT(7)
210 # define DSI0_INT_ERR_CONT_LP1 BIT(6)
211 # define DSI0_INT_ERR_CONT_LP0 BIT(5)
213 # define DSI0_INT_ERR_CONTROL BIT(4)
214 # define DSI0_INT_ERR_SYNC_ESC BIT(3)
215 # define DSI0_INT_RX2_PKT BIT(2)
216 # define DSI0_INT_RX1_PKT BIT(1)
217 # define DSI0_INT_CMD_PKT BIT(0)
228 # define DSI1_INT_PHY_D3_ULPS BIT(30)
229 # define DSI1_INT_PHY_D3_STOP BIT(29)
230 # define DSI1_INT_PHY_D2_ULPS BIT(28)
231 # define DSI1_INT_PHY_D2_STOP BIT(27)
232 # define DSI1_INT_PHY_D1_ULPS BIT(26)
233 # define DSI1_INT_PHY_D1_STOP BIT(25)
234 # define DSI1_INT_PHY_D0_ULPS BIT(24)
235 # define DSI1_INT_PHY_D0_STOP BIT(23)
236 # define DSI1_INT_FIFO_ERR BIT(22)
237 # define DSI1_INT_PHY_DIR_RTF BIT(21)
238 # define DSI1_INT_PHY_RXLPDT BIT(20)
239 # define DSI1_INT_PHY_RXTRIG BIT(19)
240 # define DSI1_INT_PHY_D0_LPDT BIT(18)
241 # define DSI1_INT_PHY_DIR_FTR BIT(17)
244 # define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
245 # define DSI1_INT_PHY_CLOCK_HS BIT(15)
246 # define DSI1_INT_PHY_CLOCK_STOP BIT(14)
249 # define DSI1_INT_PR_TO BIT(13)
250 # define DSI1_INT_TA_TO BIT(12)
251 # define DSI1_INT_LPRX_TO BIT(11)
252 # define DSI1_INT_HSTX_TO BIT(10)
255 # define DSI1_INT_ERR_CONT_LP1 BIT(9)
256 # define DSI1_INT_ERR_CONT_LP0 BIT(8)
259 # define DSI1_INT_ERR_CONTROL BIT(7)
262 # define DSI1_INT_ERR_SYNC_ESC BIT(6)
266 # define DSI1_INT_RXPKT2 BIT(5)
271 # define DSI1_INT_RXPKT1 BIT(4)
272 # define DSI1_INT_TXPKT2_DONE BIT(3)
273 # define DSI1_INT_TXPKT2_END BIT(2)
275 # define DSI1_INT_TXPKT1_DONE BIT(1)
277 # define DSI1_INT_TXPKT1_END BIT(0)
296 # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
297 # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
298 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
299 # define DSI1_PHYC_CLANE_ULPS BIT(17)
300 # define DSI1_PHYC_CLANE_ENABLE BIT(16)
301 # define DSI_PHYC_DLANE3_ULPS BIT(13)
302 # define DSI_PHYC_DLANE3_ENABLE BIT(12)
303 # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
304 # define DSI0_PHYC_CLANE_ULPS BIT(9)
305 # define DSI_PHYC_DLANE2_ULPS BIT(9)
306 # define DSI0_PHYC_CLANE_ENABLE BIT(8)
307 # define DSI_PHYC_DLANE2_ENABLE BIT(8)
308 # define DSI_PHYC_DLANE1_ULPS BIT(5)
309 # define DSI_PHYC_DLANE1_ENABLE BIT(4)
310 # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
311 # define DSI_PHYC_DLANE0_ULPS BIT(1)
312 # define DSI_PHYC_DLANE0_ENABLE BIT(0)
324 # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
325 # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
326 # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
341 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
342 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
343 # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
344 # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
345 # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
346 # define DSI1_PHY_AFEC0_RESET BIT(13)
347 # define DSI1_PHY_AFEC0_PD BIT(12)
348 # define DSI0_PHY_AFEC0_RESET BIT(11)
349 # define DSI1_PHY_AFEC0_PD_BG BIT(11)
350 # define DSI0_PHY_AFEC0_PD BIT(10)
351 # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10)
352 # define DSI0_PHY_AFEC0_PD_BG BIT(9)
353 # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
354 # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
355 # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8)
381 # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
382 # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
383 # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
384 # define DSI_CTRL_SOFT_RESET_CFG BIT(10)
385 # define DSI_CTRL_CAL_BYTE BIT(9)
386 # define DSI_CTRL_INV_BYTE BIT(8)
387 # define DSI_CTRL_CLR_LDF BIT(7)
388 # define DSI0_CTRL_CLR_PBCF BIT(6)
389 # define DSI1_CTRL_CLR_RXF BIT(6)
390 # define DSI0_CTRL_CLR_CPBCF BIT(5)
391 # define DSI1_CTRL_CLR_PDF BIT(5)
392 # define DSI0_CTRL_CLR_PDF BIT(4)
393 # define DSI1_CTRL_CLR_CDF BIT(4)
394 # define DSI0_CTRL_CLR_CDF BIT(3)
395 # define DSI0_CTRL_CTRL2 BIT(2)
396 # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
397 # define DSI0_CTRL_CTRL1 BIT(1)
398 # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
399 # define DSI0_CTRL_CTRL0 BIT(0)
400 # define DSI1_CTRL_EN BIT(0)
419 * writing a 1 clears the bit.
422 # define DSI1_STAT_PHY_D3_ULPS BIT(31)
423 # define DSI1_STAT_PHY_D3_STOP BIT(30)
424 # define DSI1_STAT_PHY_D2_ULPS BIT(29)
425 # define DSI1_STAT_PHY_D2_STOP BIT(28)
426 # define DSI1_STAT_PHY_D1_ULPS BIT(27)
427 # define DSI1_STAT_PHY_D1_STOP BIT(26)
428 # define DSI1_STAT_PHY_D0_ULPS BIT(25)
429 # define DSI1_STAT_PHY_D0_STOP BIT(24)
430 # define DSI1_STAT_FIFO_ERR BIT(23)
431 # define DSI1_STAT_PHY_RXLPDT BIT(22)
432 # define DSI1_STAT_PHY_RXTRIG BIT(21)
433 # define DSI1_STAT_PHY_D0_LPDT BIT(20)
435 # define DSI1_STAT_PHY_DIR BIT(19)
436 # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
437 # define DSI1_STAT_PHY_CLOCK_HS BIT(17)
438 # define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
439 # define DSI1_STAT_PR_TO BIT(15)
440 # define DSI1_STAT_TA_TO BIT(14)
441 # define DSI1_STAT_LPRX_TO BIT(13)
442 # define DSI1_STAT_HSTX_TO BIT(12)
443 # define DSI1_STAT_ERR_CONT_LP1 BIT(11)
444 # define DSI1_STAT_ERR_CONT_LP0 BIT(10)
445 # define DSI1_STAT_ERR_CONTROL BIT(9)
446 # define DSI1_STAT_ERR_SYNC_ESC BIT(8)
447 # define DSI1_STAT_RXPKT2 BIT(7)
448 # define DSI1_STAT_RXPKT1 BIT(6)
449 # define DSI1_STAT_TXPKT2_BUSY BIT(5)
450 # define DSI1_STAT_TXPKT2_DONE BIT(4)
451 # define DSI1_STAT_TXPKT2_END BIT(3)
452 # define DSI1_STAT_TXPKT1_BUSY BIT(2)
453 # define DSI1_STAT_TXPKT1_DONE BIT(1)
454 # define DSI1_STAT_TXPKT1_END BIT(0)
519 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
520 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
575 u32 divider; member
581 struct clk *escape_clock;
583 /* Input clock to the analog PHY, used to generate the DSI bit
586 struct clk *pll_phy_clock;
596 struct clk *pixel_clock;
616 struct drm_device *drm = dsi->bridge.dev; in dsi_dma_workaround_write()
617 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
626 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
630 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
632 tx = chan->device->device_prep_dma_memcpy(chan, in dsi_dma_workaround_write()
633 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
634 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
641 cookie = tx->tx_submit(tx); in dsi_dma_workaround_write()
655 readl(dsi->regs + (offset)); \
660 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
662 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
663 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit) argument
730 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
733 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
734 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
735 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
738 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
739 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
740 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
743 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
744 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
745 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
757 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
776 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
817 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_post_disable()
819 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_bridge_post_disable()
820 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_bridge_post_disable()
821 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_bridge_post_disable()
826 /* Extends the mode's blank intervals to handle BCM2835's integer-only
827 * DSI PLL divider.
831 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
832 * the pixel clock), only has an integer divider off of DSI.
836 * higher-than-expected clock rate to the panel, but that's what the
844 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_bridge_mode_fixup()
846 unsigned long pixel_clock_hz = mode->clock * 1000; in vc4_dsi_bridge_mode_fixup()
847 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_bridge_mode_fixup()
848 int divider; in vc4_dsi_bridge_mode_fixup() local
850 /* Find what divider gets us a faster clock than the requested in vc4_dsi_bridge_mode_fixup()
853 for (divider = 1; divider < 255; divider++) { in vc4_dsi_bridge_mode_fixup()
854 if (parent_rate / (divider + 1) < pll_clock) in vc4_dsi_bridge_mode_fixup()
858 /* Now that we've picked a PLL divider, calculate back to its in vc4_dsi_bridge_mode_fixup()
861 pll_clock = parent_rate / divider; in vc4_dsi_bridge_mode_fixup()
862 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_bridge_mode_fixup()
864 adjusted_mode->clock = pixel_clock_hz / 1000; in vc4_dsi_bridge_mode_fixup()
867 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / in vc4_dsi_bridge_mode_fixup()
868 mode->clock; in vc4_dsi_bridge_mode_fixup()
869 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; in vc4_dsi_bridge_mode_fixup()
870 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; in vc4_dsi_bridge_mode_fixup()
878 struct drm_atomic_state *state = old_state->base.state; in vc4_dsi_bridge_pre_enable()
881 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_pre_enable()
897 drm_err(bridge->dev, "Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_bridge_pre_enable()
902 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_pre_enable()
903 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_bridge_pre_enable()
904 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_pre_enable()
912 bridge->encoder); in vc4_dsi_bridge_pre_enable()
913 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; in vc4_dsi_bridge_pre_enable()
915 mode = &crtc_state->adjusted_mode; in vc4_dsi_bridge_pre_enable()
917 pixel_clock_hz = mode->clock * 1000; in vc4_dsi_bridge_pre_enable()
920 * PLLD_DSI1 is an integer divider and its rate selection will in vc4_dsi_bridge_pre_enable()
923 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_bridge_pre_enable()
924 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_bridge_pre_enable()
926 dev_err(&dsi->pdev->dev, in vc4_dsi_bridge_pre_enable()
943 if (dsi->variant->port == 0) { in vc4_dsi_bridge_pre_enable()
947 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
950 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_bridge_pre_enable()
971 if (dsi->lanes < 4) in vc4_dsi_bridge_pre_enable()
973 if (dsi->lanes < 3) in vc4_dsi_bridge_pre_enable()
975 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
988 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_bridge_pre_enable()
990 drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n", in vc4_dsi_bridge_pre_enable()
995 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
997 drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret); in vc4_dsi_bridge_pre_enable()
1001 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
1011 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_bridge_pre_enable()
1017 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_bridge_pre_enable()
1019 drm_err(bridge->dev, "Failed to turn on DSI pixel clock: %d\n", ret); in vc4_dsi_bridge_pre_enable()
1062 /* T_INIT is how long STOP is driven after power-up to in vc4_dsi_bridge_pre_enable()
1063 * indicate to the slave (also coming out of power-up) that in vc4_dsi_bridge_pre_enable()
1066 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and in vc4_dsi_bridge_pre_enable()
1087 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1088 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1089 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1091 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_bridge_pre_enable()
1093 (dsi->variant->port == 0 ? in vc4_dsi_bridge_pre_enable()
1094 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : in vc4_dsi_bridge_pre_enable()
1095 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); in vc4_dsi_bridge_pre_enable()
1119 if (dsi->variant->port == 0) in vc4_dsi_bridge_pre_enable()
1131 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_bridge_pre_enable()
1133 VC4_SET_FIELD(dsi->divider, in vc4_dsi_bridge_pre_enable()
1135 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_bridge_pre_enable()
1157 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_enable()
1158 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_bridge_enable()
1159 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_enable()
1169 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, in vc4_dsi_bridge_attach()
1170 &dsi->bridge, flags); in vc4_dsi_bridge_attach()
1177 struct drm_device *drm = dsi->bridge.dev; in vc4_dsi_host_transfer()
1181 bool is_long = mipi_dsi_packet_format_is_long(msg->type); in vc4_dsi_host_transfer()
1192 * The command FIFO takes byte-oriented data, but is of in vc4_dsi_host_transfer()
1206 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / in vc4_dsi_host_transfer()
1215 if (msg->rx_len) { in vc4_dsi_host_transfer()
1235 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in vc4_dsi_host_transfer()
1255 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1256 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1257 if (dsi->variant->port == 0) { in vc4_dsi_host_transfer()
1260 if (msg->rx_len) { in vc4_dsi_host_transfer()
1272 if (msg->rx_len) { in vc4_dsi_host_transfer()
1285 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1287 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1288 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1290 ret = -ETIMEDOUT; in vc4_dsi_host_transfer()
1292 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1300 if (ret == 0 && msg->rx_len) { in vc4_dsi_host_transfer()
1302 u8 *msg_rx = msg->rx_buf; in vc4_dsi_host_transfer()
1308 if (rxlen != msg->rx_len) { in vc4_dsi_host_transfer()
1310 rxlen, (int)msg->rx_len); in vc4_dsi_host_transfer()
1311 ret = -ENXIO; in vc4_dsi_host_transfer()
1315 for (i = 0; i < msg->rx_len; i++) in vc4_dsi_host_transfer()
1322 if (msg->rx_len > 1) { in vc4_dsi_host_transfer()
1352 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1353 dsi->channel = device->channel; in vc4_dsi_host_attach()
1354 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1356 switch (device->format) { in vc4_dsi_host_attach()
1358 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1359 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1362 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1363 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1366 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1367 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1370 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1371 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1374 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1375 dsi->format); in vc4_dsi_host_attach()
1379 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1380 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1385 drm_bridge_add(&dsi->bridge); in vc4_dsi_host_attach()
1387 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_attach()
1389 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_attach()
1401 component_del(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_detach()
1402 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_detach()
1426 struct drm_device *drm = encoder->dev; in vc4_dsi_late_register()
1429 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset); in vc4_dsi_late_register()
1461 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1462 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1463 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1468 irqreturn_t *ret, u32 stat, u32 bit, in dsi_handle_error() argument
1471 if (!(stat & bit)) in dsi_handle_error()
1474 drm_err(dsi->bridge.dev, "DSI%d: %s error\n", dsi->variant->port, in dsi_handle_error()
1525 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : in vc4_dsi_irq_handler()
1528 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1531 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1532 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1540 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1541 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1547 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1548 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1559 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1560 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1564 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1565 return -ENOMEM; in vc4_dsi_init_phy_clocks()
1566 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1569 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1575 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1586 fix->mult = 1; in vc4_dsi_init_phy_clocks()
1587 fix->div = phy_clocks[i].div; in vc4_dsi_init_phy_clocks()
1588 fix->hw.init = &init; in vc4_dsi_init_phy_clocks()
1596 ret = devm_clk_hw_register(dev, &fix->hw); in vc4_dsi_init_phy_clocks()
1600 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1603 return of_clk_add_hw_provider(dev->of_node, in vc4_dsi_init_phy_clocks()
1605 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1611 struct device *dev = &dsi->pdev->dev; in vc4_dsi_dma_mem_release()
1613 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr); in vc4_dsi_dma_mem_release()
1614 dsi->reg_dma_mem = NULL; in vc4_dsi_dma_mem_release()
1621 dma_release_channel(dsi->reg_dma_chan); in vc4_dsi_dma_chan_release()
1622 dsi->reg_dma_chan = NULL; in vc4_dsi_dma_chan_release()
1635 kref_get(&dsi->kref); in vc4_dsi_get()
1640 kref_put(&dsi->kref, &vc4_dsi_release); in vc4_dsi_put()
1655 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_bind()
1664 dsi->variant = of_device_get_match_data(dev); in vc4_dsi_bind()
1666 dsi->encoder.type = dsi->variant->port ? in vc4_dsi_bind()
1669 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1670 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1671 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1673 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1674 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1675 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1680 return -ENODEV; in vc4_dsi_bind()
1687 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1690 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1691 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1693 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1695 return -ENOMEM; in vc4_dsi_bind()
1705 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1706 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1707 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1708 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1722 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1726 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1727 /* At startup enable error-reporting interrupts and nothing else. */ in vc4_dsi_bind()
1732 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1742 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1747 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1748 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1749 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1750 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1755 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1756 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1757 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1758 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1763 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1764 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1765 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1766 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1771 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0); in vc4_dsi_bind()
1772 if (IS_ERR(dsi->out_bridge)) in vc4_dsi_bind()
1773 return PTR_ERR(dsi->out_bridge); in vc4_dsi_bind()
1776 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1797 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); in vc4_dsi_bind()
1810 struct device *dev = &pdev->dev; in vc4_dsi_dev_probe()
1815 return -ENOMEM; in vc4_dsi_dev_probe()
1818 kref_init(&dsi->kref); in vc4_dsi_dev_probe()
1820 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1821 dsi->bridge.funcs = &vc4_dsi_bridge_funcs; in vc4_dsi_dev_probe()
1823 dsi->bridge.of_node = dev->of_node; in vc4_dsi_dev_probe()
1825 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; in vc4_dsi_dev_probe()
1826 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1827 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1828 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1835 struct device *dev = &pdev->dev; in vc4_dsi_dev_remove()
1838 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()