Lines Matching full:v3d
5 * DOC: Broadcom V3D scheduling
121 v3d_switch_perfmon(struct v3d_dev *v3d, struct v3d_job *job) in v3d_switch_perfmon() argument
123 struct v3d_perfmon *perfmon = v3d->global_perfmon; in v3d_switch_perfmon()
128 if (perfmon == v3d->active_perfmon) in v3d_switch_perfmon()
131 if (perfmon != v3d->active_perfmon) in v3d_switch_perfmon()
132 v3d_perfmon_stop(v3d, v3d->active_perfmon, true); in v3d_switch_perfmon()
134 if (perfmon && v3d->active_perfmon != perfmon) in v3d_switch_perfmon()
135 v3d_perfmon_start(v3d, perfmon); in v3d_switch_perfmon()
141 struct v3d_dev *v3d = job->v3d; in v3d_job_start_stats() local
143 struct v3d_stats *global_stats = &v3d->queue[queue].stats; in v3d_job_start_stats()
199 struct v3d_dev *v3d = job->v3d; in v3d_job_update_stats() local
201 struct v3d_stats *global_stats = &v3d->queue[queue].stats; in v3d_job_update_stats()
224 struct v3d_dev *v3d = job->base.v3d; in v3d_bin_job_run() local
225 struct drm_device *dev = &v3d->drm; in v3d_bin_job_run()
230 spin_lock_irqsave(&v3d->job_lock, irqflags); in v3d_bin_job_run()
231 v3d->bin_job = NULL; in v3d_bin_job_run()
232 spin_unlock_irqrestore(&v3d->job_lock, irqflags); in v3d_bin_job_run()
239 spin_lock_irqsave(&v3d->job_lock, irqflags); in v3d_bin_job_run()
240 v3d->bin_job = job; in v3d_bin_job_run()
245 spin_unlock_irqrestore(&v3d->job_lock, irqflags); in v3d_bin_job_run()
247 v3d_invalidate_caches(v3d); in v3d_bin_job_run()
249 fence = v3d_fence_create(v3d, V3D_BIN); in v3d_bin_job_run()
261 v3d_switch_perfmon(v3d, &job->base); in v3d_bin_job_run()
284 struct v3d_dev *v3d = job->base.v3d; in v3d_render_job_run() local
285 struct drm_device *dev = &v3d->drm; in v3d_render_job_run()
289 v3d->render_job = NULL; in v3d_render_job_run()
293 v3d->render_job = job; in v3d_render_job_run()
301 v3d_invalidate_caches(v3d); in v3d_render_job_run()
303 fence = v3d_fence_create(v3d, V3D_RENDER); in v3d_render_job_run()
315 v3d_switch_perfmon(v3d, &job->base); in v3d_render_job_run()
332 struct v3d_dev *v3d = job->base.v3d; in v3d_tfu_job_run() local
333 struct drm_device *dev = &v3d->drm; in v3d_tfu_job_run()
337 v3d->tfu_job = NULL; in v3d_tfu_job_run()
341 v3d->tfu_job = job; in v3d_tfu_job_run()
343 fence = v3d_fence_create(v3d, V3D_TFU); in v3d_tfu_job_run()
355 V3D_WRITE(V3D_TFU_IIA(v3d->ver), job->args.iia); in v3d_tfu_job_run()
356 V3D_WRITE(V3D_TFU_IIS(v3d->ver), job->args.iis); in v3d_tfu_job_run()
357 V3D_WRITE(V3D_TFU_ICA(v3d->ver), job->args.ica); in v3d_tfu_job_run()
358 V3D_WRITE(V3D_TFU_IUA(v3d->ver), job->args.iua); in v3d_tfu_job_run()
359 V3D_WRITE(V3D_TFU_IOA(v3d->ver), job->args.ioa); in v3d_tfu_job_run()
360 if (v3d->ver >= 71) in v3d_tfu_job_run()
362 V3D_WRITE(V3D_TFU_IOS(v3d->ver), job->args.ios); in v3d_tfu_job_run()
363 V3D_WRITE(V3D_TFU_COEF0(v3d->ver), job->args.coef[0]); in v3d_tfu_job_run()
364 if (v3d->ver >= 71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) { in v3d_tfu_job_run()
365 V3D_WRITE(V3D_TFU_COEF1(v3d->ver), job->args.coef[1]); in v3d_tfu_job_run()
366 V3D_WRITE(V3D_TFU_COEF2(v3d->ver), job->args.coef[2]); in v3d_tfu_job_run()
367 V3D_WRITE(V3D_TFU_COEF3(v3d->ver), job->args.coef[3]); in v3d_tfu_job_run()
370 V3D_WRITE(V3D_TFU_ICFG(v3d->ver), job->args.icfg | V3D_TFU_ICFG_IOC); in v3d_tfu_job_run()
379 struct v3d_dev *v3d = job->base.v3d; in v3d_csd_job_run() local
380 struct drm_device *dev = &v3d->drm; in v3d_csd_job_run()
385 v3d->csd_job = NULL; in v3d_csd_job_run()
389 v3d->csd_job = job; in v3d_csd_job_run()
391 v3d_invalidate_caches(v3d); in v3d_csd_job_run()
393 fence = v3d_fence_create(v3d, V3D_CSD); in v3d_csd_job_run()
404 v3d_switch_perfmon(v3d, &job->base); in v3d_csd_job_run()
406 csd_cfg0_reg = V3D_CSD_QUEUED_CFG0(v3d->ver); in v3d_csd_job_run()
410 /* Although V3D 7.1 has an eighth configuration register, we are not in v3d_csd_job_run()
415 if (v3d->ver >= 71) in v3d_csd_job_run()
431 struct v3d_dev *v3d = job->base.v3d; in v3d_rewrite_csd_job_wg_counts_from_indirect() local
449 /* V3D 7.1.6 and later don't subtract 1 from the number of batches */ in v3d_rewrite_csd_job_wg_counts_from_indirect()
450 if (v3d->ver < 71 || (v3d->ver == 71 && v3d->rev < 6)) in v3d_rewrite_csd_job_wg_counts_from_indirect()
574 struct v3d_dev *v3d = job->base.v3d; in v3d_reset_performance_queries() local
586 v3d_perfmon_stop(v3d, perfmon, false); in v3d_reset_performance_queries()
606 struct v3d_dev *v3d = job->base.v3d; in v3d_write_performance_query_result() local
621 v3d_perfmon_stop(v3d, perfmon, true); in v3d_write_performance_query_result()
684 struct v3d_dev *v3d = job->base.v3d; in v3d_cpu_job_run() local
686 v3d->cpu_job = job; in v3d_cpu_job_run()
694 trace_v3d_cpu_job_begin(&v3d->drm, job->job_type); in v3d_cpu_job_run()
698 trace_v3d_cpu_job_end(&v3d->drm, job->job_type); in v3d_cpu_job_run()
708 struct v3d_dev *v3d = job->v3d; in v3d_cache_clean_job_run() local
712 v3d_clean_caches(v3d); in v3d_cache_clean_job_run()
720 v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job) in v3d_gpu_reset_for_timeout() argument
724 mutex_lock(&v3d->reset_lock); in v3d_gpu_reset_for_timeout()
728 drm_sched_stop(&v3d->queue[q].sched, sched_job); in v3d_gpu_reset_for_timeout()
734 v3d_reset(v3d); in v3d_gpu_reset_for_timeout()
737 drm_sched_resubmit_jobs(&v3d->queue[q].sched); in v3d_gpu_reset_for_timeout()
741 drm_sched_start(&v3d->queue[q].sched, 0); in v3d_gpu_reset_for_timeout()
744 mutex_unlock(&v3d->reset_lock); in v3d_gpu_reset_for_timeout()
759 struct v3d_dev *v3d = job->v3d; in v3d_cl_job_timedout() local
769 return v3d_gpu_reset_for_timeout(v3d, sched_job); in v3d_cl_job_timedout()
795 return v3d_gpu_reset_for_timeout(job->v3d, sched_job); in v3d_generic_job_timedout()
802 struct v3d_dev *v3d = job->base.v3d; in v3d_csd_job_timedout() local
803 u32 batches = V3D_CORE_READ(0, V3D_CSD_CURRENT_CFG4(v3d->ver)); in v3d_csd_job_timedout()
813 return v3d_gpu_reset_for_timeout(v3d, sched_job); in v3d_csd_job_timedout()
853 v3d_sched_init(struct v3d_dev *v3d) in v3d_sched_init() argument
860 ret = drm_sched_init(&v3d->queue[V3D_BIN].sched, in v3d_sched_init()
865 NULL, "v3d_bin", v3d->drm.dev); in v3d_sched_init()
869 ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched, in v3d_sched_init()
874 NULL, "v3d_render", v3d->drm.dev); in v3d_sched_init()
878 ret = drm_sched_init(&v3d->queue[V3D_TFU].sched, in v3d_sched_init()
883 NULL, "v3d_tfu", v3d->drm.dev); in v3d_sched_init()
887 if (v3d_has_csd(v3d)) { in v3d_sched_init()
888 ret = drm_sched_init(&v3d->queue[V3D_CSD].sched, in v3d_sched_init()
893 NULL, "v3d_csd", v3d->drm.dev); in v3d_sched_init()
897 ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched, in v3d_sched_init()
902 NULL, "v3d_cache_clean", v3d->drm.dev); in v3d_sched_init()
907 ret = drm_sched_init(&v3d->queue[V3D_CPU].sched, in v3d_sched_init()
912 NULL, "v3d_cpu", v3d->drm.dev); in v3d_sched_init()
919 v3d_sched_fini(v3d); in v3d_sched_init()
924 v3d_sched_fini(struct v3d_dev *v3d) in v3d_sched_fini() argument
929 if (v3d->queue[q].sched.ready) in v3d_sched_fini()
930 drm_sched_fini(&v3d->queue[q].sched); in v3d_sched_fini()