5  * DOC: Interrupt management for the V3D engine
41 	struct v3d_dev *v3d =  in v3d_overflow_mem_work()  local
43 	struct drm_device *dev = &v3d->drm;  in v3d_overflow_mem_work()
63 	spin_lock_irqsave(&v3d->job_lock, irqflags);  in v3d_overflow_mem_work()
64 	if (!v3d->bin_job) {  in v3d_overflow_mem_work()
65 		spin_unlock_irqrestore(&v3d->job_lock, irqflags);  in v3d_overflow_mem_work()
70 	list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);  in v3d_overflow_mem_work()
71 	spin_unlock_irqrestore(&v3d->job_lock, irqflags);  in v3d_overflow_mem_work()
73 	v3d_mmu_flush_all(v3d);  in v3d_overflow_mem_work()
85 	struct v3d_dev *v3d = arg;  in v3d_irq()  local
97 		 * add more memory.  Also, as of V3D 4.1, FLDONE won't  in v3d_irq()
100 		schedule_work(&v3d->overflow_mem_work);  in v3d_irq()
106 			to_v3d_fence(v3d->bin_job->base.irq_fence);  in v3d_irq()
108 		v3d_job_update_stats(&v3d->bin_job->base, V3D_BIN);  in v3d_irq()
109 		trace_v3d_bcl_irq(&v3d->drm, fence->seqno);  in v3d_irq()
111 		v3d->bin_job = NULL;  in v3d_irq()
119 			to_v3d_fence(v3d->render_job->base.irq_fence);  in v3d_irq()
121 		v3d_job_update_stats(&v3d->render_job->base, V3D_RENDER);  in v3d_irq()
122 		trace_v3d_rcl_irq(&v3d->drm, fence->seqno);  in v3d_irq()
124 		v3d->render_job = NULL;  in v3d_irq()
130 	if (intsts & V3D_INT_CSDDONE(v3d->ver)) {  in v3d_irq()
132 			to_v3d_fence(v3d->csd_job->base.irq_fence);  in v3d_irq()
134 		v3d_job_update_stats(&v3d->csd_job->base, V3D_CSD);  in v3d_irq()
135 		trace_v3d_csd_irq(&v3d->drm, fence->seqno);  in v3d_irq()
137 		v3d->csd_job = NULL;  in v3d_irq()
146 	if (v3d->ver < 71 && (intsts & V3D_INT_GMPV))  in v3d_irq()
147 		dev_err(v3d->drm.dev, "GMP violation\n");  in v3d_irq()
149 	/* V3D 4.2 wires the hub and core IRQs together, so if we &  in v3d_irq()
152 	if (v3d->single_irq_line && status == IRQ_NONE)  in v3d_irq()
161 	struct v3d_dev *v3d = arg;  in v3d_hub_irq()  local
172 			to_v3d_fence(v3d->tfu_job->base.irq_fence);  in v3d_hub_irq()
174 		v3d_job_update_stats(&v3d->tfu_job->base, V3D_TFU);  in v3d_hub_irq()
175 		trace_v3d_tfu_irq(&v3d->drm, fence->seqno);  in v3d_hub_irq()
177 		v3d->tfu_job = NULL;  in v3d_hub_irq()
188 				(v3d->va_width - 32));  in v3d_hub_irq()
203 		if (v3d->ver >= 41) {  in v3d_hub_irq()
209 		dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",  in v3d_hub_irq()
220 	if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) {  in v3d_hub_irq()
221 		dev_err(v3d->drm.dev, "GMP Violation\n");  in v3d_hub_irq()
229 v3d_irq_init(struct v3d_dev *v3d)  in v3d_irq_init()  argument
233 	INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);  in v3d_irq_init()
238 	for (core = 0; core < v3d->cores; core++)  in v3d_irq_init()
239 		V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));  in v3d_irq_init()
240 	V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));  in v3d_irq_init()
242 	irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);  in v3d_irq_init()
246 		ret = devm_request_irq(v3d->drm.dev, irq1,  in v3d_irq_init()
248 				       "v3d_core0", v3d);  in v3d_irq_init()
251 		ret = devm_request_irq(v3d->drm.dev,  in v3d_irq_init()
252 				       platform_get_irq(v3d_to_pdev(v3d), 0),  in v3d_irq_init()
254 				       "v3d_hub", v3d);  in v3d_irq_init()
258 		v3d->single_irq_line = true;  in v3d_irq_init()
260 		ret = devm_request_irq(v3d->drm.dev,  in v3d_irq_init()
261 				       platform_get_irq(v3d_to_pdev(v3d), 0),  in v3d_irq_init()
263 				       "v3d", v3d);  in v3d_irq_init()
268 	v3d_irq_enable(v3d);  in v3d_irq_init()
273 		dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);  in v3d_irq_init()
278 v3d_irq_enable(struct v3d_dev *v3d)  in v3d_irq_enable()  argument
283 	for (core = 0; core < v3d->cores; core++) {  in v3d_irq_enable()
284 		V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver));  in v3d_irq_enable()
285 		V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver));  in v3d_irq_enable()
288 	V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver));  in v3d_irq_enable()
289 	V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver));  in v3d_irq_enable()
293 v3d_irq_disable(struct v3d_dev *v3d)  in v3d_irq_disable()  argument
298 	for (core = 0; core < v3d->cores; core++)  in v3d_irq_disable()
303 	for (core = 0; core < v3d->cores; core++)  in v3d_irq_disable()
304 		V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));  in v3d_irq_disable()
305 	V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));  in v3d_irq_disable()
307 	cancel_work_sync(&v3d->overflow_mem_work);  in v3d_irq_disable()
311 void v3d_irq_reset(struct v3d_dev *v3d)  in v3d_irq_reset()  argument
313 	v3d_irq_enable(v3d);  in v3d_irq_reset()