28 #define TILCDC_PALETTE_FIRST_ENTRY		0x4000
71 	gem = drm_fb_dma_get_gem_obj(fb, 0);  in set_scanout()
73 	start = gem->dma_addr + fb->offsets[0] +  in set_scanout()
74 		crtc->y * fb->pitches[0] +  in set_scanout()
75 		crtc->x * fb->format->cpp[0];  in set_scanout()
77 	end = start + (crtc->mode.vdisplay * fb->pitches[0]);  in set_scanout()
94  * should still be loaded. The first 16-bit entry must be 0x4000 while
125 	tilcdc_clear_irqstatus(dev, 0xffffffff);  in tilcdc_crtc_load_palette()
130 	if (ret == 0)  in tilcdc_crtc_load_palette()
145 	tilcdc_clear_irqstatus(dev, 0xffffffff);  in tilcdc_crtc_enable_irqs()
219 	if (ret < 0 || tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) {  in tilcdc_crtc_set_clk()
290 	reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;  in tilcdc_crtc_set_mode()
326 	reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;  in tilcdc_crtc_set_mode()
332 	 * a value of 0 as 1  in tilcdc_crtc_set_mode()
336 		reg &= ~0x78000033;  in tilcdc_crtc_set_mode()
337 		reg |= ((hfp-1) & 0x300) >> 8;  in tilcdc_crtc_set_mode()
338 		reg |= ((hbp-1) & 0x300) >> 4;  in tilcdc_crtc_set_mode()
339 		reg |= ((hsw-1) & 0x3c0) << 21;  in tilcdc_crtc_set_mode()
344 		(((hbp-1) & 0xff) << 24) |  in tilcdc_crtc_set_mode()
345 		(((hfp-1) & 0xff) << 16) |  in tilcdc_crtc_set_mode()
346 		(((hsw-1) & 0x3f) << 10);  in tilcdc_crtc_set_mode()
348 		reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;  in tilcdc_crtc_set_mode()
351 	reg = ((mode->vdisplay - 1) & 0x3ff) |  in tilcdc_crtc_set_mode()
352 		((vbp & 0xff) << 24) |  in tilcdc_crtc_set_mode()
353 		((vfp & 0xff) << 16) |  in tilcdc_crtc_set_mode()
354 		(((vsw-1) & 0x3f) << 10);  in tilcdc_crtc_set_mode()
363 		if ((mode->vdisplay - 1) & 0x400) {  in tilcdc_crtc_set_mode()
376 		  0x000ff000 /* Palette Loading Delay bits */);  in tilcdc_crtc_set_mode()
514 	if (ret == 0)  in tilcdc_crtc_off()
638 	return 0;  in tilcdc_crtc_update_fb()
677 		return 0;  in tilcdc_crtc_atomic_check()
679 	if (state->planes[0].ptr != crtc->primary ||  in tilcdc_crtc_atomic_check()
680 	    state->planes[0].state == NULL ||  in tilcdc_crtc_atomic_check()
681 	    state->planes[0].state->crtc != crtc) {  in tilcdc_crtc_atomic_check()
686 	return 0;  in tilcdc_crtc_atomic_check()
709 	return 0;  in tilcdc_crtc_enable_vblank()
744 		tilcdc_clear_irqstatus(dev, 0xffffffff);  in tilcdc_crtc_reset()
752 		if (ret == 0)  in tilcdc_crtc_reset()
786 	if (mode->hdisplay & 0xf)  in tilcdc_crtc_mode_valid()
803 	if ((hbp-1) & ~0x3ff) {  in tilcdc_crtc_mode_valid()
808 	if ((hfp-1) & ~0x3ff) {  in tilcdc_crtc_mode_valid()
813 	if ((hsw-1) & ~0x3ff) {  in tilcdc_crtc_mode_valid()
818 	if (vbp & ~0xff) {  in tilcdc_crtc_mode_valid()
823 	if (vfp & ~0xff) {  in tilcdc_crtc_mode_valid()
828 	if ((vsw-1) & ~0x3f) {  in tilcdc_crtc_mode_valid()
951 			tilcdc_crtc->sync_lost_count = 0;  in tilcdc_crtc_irq()
957 		dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",  in tilcdc_crtc_irq()
971 		dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",  in tilcdc_crtc_irq()
986 					"%s(0x%08x): Sync lost flood detected, recovering",  in tilcdc_crtc_irq()
992 				tilcdc_crtc->sync_lost_count = 0;  in tilcdc_crtc_irq()
1011 		tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);  in tilcdc_crtc_irq()
1040 	if (ret < 0)  in tilcdc_crtc_create()
1055 	if (ret < 0)  in tilcdc_crtc_create()
1061 		crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0);  in tilcdc_crtc_create()
1071 	return 0;  in tilcdc_crtc_create()