79 		 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
82 		 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
93 	.num_vps = 1,
106 	.num_planes = 1,
155 		 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
158 		 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
182 	/* note: vid is plane_id 0 and vidl1 is plane_id 1 */
185 	.vid_order = { 1, 0 },
244 		 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
247 		 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
272 	.vid_lite = { 0, 1, 0, 1, },
273 	.vid_order = { 1, 3, 0, 2 },
292 		 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
295 		 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
319 	/* note: vid is plane_id 0 and vidl1 is plane_id 1 */
322 	.vid_order = { 1, 0 },
345 		 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
348 		 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
373 	/* note: vid is plane_id 0 and vidl1 is plane_id 1 */
376 	.vid_order = { 1, 0 },
476 	return ((1 << (start - end + 1)) - 1) << end;  in FLD_MASK()
554 	if (stat & BIT(1))  in dispc_vp_irq_from_raw()
571 		stat |= BIT(1);  in dispc_vp_irq_to_raw()
709 	dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7));  in dispc_k2g_set_irqenable()
886 		WARN_ON(1);  in dispc_read_and_clear_irqstatus()
904 		WARN_ON(1);  in dispc_set_irqenable()
909 enum dispc_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 };
997 		v = 1; break;  in dispc_set_num_datalines()
1007 		WARN_ON(1);  in dispc_set_num_datalines()
1034 	oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1);  in dispc_enable_oldi()
1096 		       FLD_VAL(hsw - 1, 7, 0) |  in dispc_vp_enable()
1097 		       FLD_VAL(hfp - 1, 19, 8) |  in dispc_vp_enable()
1098 		       FLD_VAL(hbp - 1, 31, 20));  in dispc_vp_enable()
1101 		       FLD_VAL(vsw - 1, 7, 0) |  in dispc_vp_enable()
1135 		       FLD_VAL(mode->hdisplay - 1, 11, 0) |  in dispc_vp_enable()
1136 		       FLD_VAL(mode->vdisplay - 1, 27, 16));  in dispc_vp_enable()
1138 	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);  in dispc_vp_enable()
1163 	VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);  in dispc_vp_go()
1170 	u16 c12;  in c8_to_c12()  local
1172 	c12 = c8 << 4;  in c8_to_c12()
1176 		/* Copy c8 4 MSB to 4 LSB for full scale c12 */  in c8_to_c12()
1177 		c12 |= c8 >> 4;  in c8_to_c12()
1180 		c12 |= 0xF;  in c8_to_c12()
1187 	return c12;  in c8_to_c12()
1269 	if (hsw < 1 || hsw > 256 ||  in dispc_vp_mode_valid()
1270 	    hfp < 1 || hfp > 4096 ||  in dispc_vp_mode_valid()
1271 	    hbp < 1 || hbp > 4096)  in dispc_vp_mode_valid()
1274 	if (vsw < 1 || vsw > 256 ||  in dispc_vp_mode_valid()
1362 			hw_plane, 4, 1);  in dispc_am65x_ovr_set_plane()
1374 			hw_plane, 4, 1);  in dispc_j721e_ovr_set_plane()
1400 		WARN_ON(1);  in dispc_ovr_set_plane()
1439 	enum { CLIP_LIMITED_RANGE = 0, CLIP_FULL_RANGE = 1, } cliping;
1449 	regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]);  in dispc_csc_offset_regval()
1451 	regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]);  in dispc_csc_offset_regval()
1460 	regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]);  in dispc_csc_yuv2rgb_regval()
1472 	regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]);  in dispc_csc_rgb2yuv_regval()
1484 	regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]);  in dispc_csc_cpr_regval()
1498 		DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1),  in dispc_k2g_vid_write_csc()
1521 		DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1),  in dispc_k3_vid_write_csc()
1690 		u32 c12;  in dispc_vid_write_fir_coefs()  local
1694 		c12 = FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20);  in dispc_vid_write_fir_coefs()
1696 		dispc_vid_write(dispc, hw_plane, reg, c12);  in dispc_vid_write_fir_coefs()
1734 	sp->xinc = 1;  in dispc_vid_calc_scaling()
1735 	sp->yinc = 1;  in dispc_vid_calc_scaling()
1748 		sp->in_w_uv >>= 1;  in dispc_vid_calc_scaling()
1752 			sp->in_h_uv >>= 1;  in dispc_vid_calc_scaling()
1774 		if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) {  in dispc_vid_calc_scaling()
1782 		if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) {  in dispc_vid_calc_scaling()
1789 					"%s: X-scaling factor %u/%u < 1/%u\n",  in dispc_vid_calc_scaling()
1817 			sp->in_w &= ~1;  in dispc_vid_calc_scaling()
1825 		if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) {  in dispc_vid_calc_scaling()
1833 		if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) {  in dispc_vid_calc_scaling()
1994 					6, 1);  in dispc_plane_set_pixel_format()
1999 	WARN_ON(1);  in dispc_plane_set_pixel_format()
2013 	if (pixels == 1)  in pixinc()
2014 		return 1;  in pixinc()
2015 	else if (pixels > 1)  in pixinc()
2016 		return 1 + (pixels - 1) * ps;  in pixinc()
2018 		return 1 - (-pixels + 1) * ps;  in pixinc()
2020 	WARN_ON(1);  in pixinc()
2088 	gem = drm_fb_dma_get_gem_obj(fb, 1);  in dispc_plane_state_p_uv_addr()
2090 	return gem->dma_addr + fb->offsets[1] +  in dispc_plane_state_p_uv_addr()
2091 		(x * fb->format->cpp[1] / fb->format->hsub) +  in dispc_plane_state_p_uv_addr()
2092 		(y * fb->pitches[1] / fb->format->vsub);  in dispc_plane_state_p_uv_addr()
2116 			(scale.in_w - 1) | ((scale.in_h - 1) << 16));  in dispc_plane_setup()
2127 			pixinc(1 + (scale.yinc * fb_width -  in dispc_plane_setup()
2132 		u16 cpp_uv = state->fb->format->cpp[1];  in dispc_plane_setup()
2133 		u32 fb_width_uv = state->fb->pitches[1] / cpp_uv;  in dispc_plane_setup()
2146 				pixinc(1 + (scale.yinc * fb_width_uv -  in dispc_plane_setup()
2153 				(state->crtc_w - 1) |  in dispc_plane_setup()
2154 				((state->crtc_h - 1) << 16));  in dispc_plane_setup()
2171 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,  in dispc_plane_setup()
2209 	REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);  in dispc_k2g_plane_init()
2219 		thr_high = size - 1;  in dispc_k2g_plane_init()
2247 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,  in dispc_k2g_plane_init()
2255 	u32 cba_lo_pri = 1;  in dispc_k3_plane_init()
2264 	REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);  in dispc_k3_plane_init()
2274 		thr_high = size - 1;  in dispc_k3_plane_init()
2316 		WARN_ON(1);  in dispc_plane_init()
2328 		VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);  in dispc_vp_init()
2404 			v |= 1 << 31;  in dispc_j721e_vp_write_gamma_table()
2426 		WARN_ON(1);  in dispc_vp_write_gamma_table()
2459 	for (i = 0; i < length - 1; ++i) {  in dispc_vp_set_gamma()
2460 		unsigned int first = i * (hwlen - 1) / (length - 1);  in dispc_vp_set_gamma()
2461 		unsigned int last = (i + 1) * (hwlen - 1) / (length - 1);  in dispc_vp_set_gamma()
2470 			r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w;  in dispc_vp_set_gamma()
2471 			g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w;  in dispc_vp_set_gamma()
2472 			b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w;  in dispc_vp_set_gamma()
2488 	u64 sign_bit = 1ULL << 63;  in dispc_S31_32_to_s2_8()
2507 	cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]);  in dispc_k2g_cpr_from_ctm()
2524 	regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]);  in dispc_k2g_vp_csc_cpr_regval()
2557 		cprenable = 1;  in dispc_k2g_vp_set_ctm()
2566 	u64 sign_bit = 1ULL << 63;  in dispc_S31_32_to_s3_8()
2585 	cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]);  in dispc_csc_from_ctm()
2623 		colorconvenable = 1;  in dispc_k3_vp_set_ctm()
2689 		REG_GET(dispc, DSS_SYSSTATUS, 1, 1),  in dispc_runtime_resume()
2792 	REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);  in dispc_softreset()
2795 				 val, val & 1, 100, 5000);  in dispc_softreset()