Lines Matching +full:lvds +full:- +full:4 +full:bits

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6  * Boris Brezillon <boris.brezillon@free-electrons.com>
7  * Maxime Ripard <maxime.ripard@free-electrons.com>
27 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)		BIT(31 - (pipe))
30 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe)		BIT(15 - (pipe))
40 #define SUN4I_TCON0_FRM_CTL_MODE_B			BIT(4)
57 #define SUN4I_TCON0_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
58 #define SUN4I_TCON0_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
67 #define SUN4I_TCON0_BASIC0_X(width)			((((width) - 1) & 0xfff) << 16)
68 #define SUN4I_TCON0_BASIC0_Y(height)			(((height) - 1) & 0xfff)
71 #define SUN4I_TCON0_BASIC1_H_TOTAL(total)		((((total) - 1) & 0x1fff) << 16)
72 #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
76 #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
79 #define SUN4I_TCON0_BASIC3_H_SYNC(width)		((((width) - 1) & 0x7ff) << 16)
80 #define SUN4I_TCON0_BASIC3_V_SYNC(height)		(((height) - 1) & 0x7ff)
107 #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK		BIT(4)
108 #define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL		(1 << 4)
109 #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV			(0 << 4)
129 #define SUN4I_TCON1_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
130 #define SUN4I_TCON1_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK)
134 #define SUN4I_TCON1_BASIC0_X(width)			((((width) - 1) & 0xfff) << 16)
135 #define SUN4I_TCON1_BASIC0_Y(height)			(((height) - 1) & 0xfff)
138 #define SUN4I_TCON1_BASIC1_X(width)			((((width) - 1) & 0xfff) << 16)
139 #define SUN4I_TCON1_BASIC1_Y(height)			(((height) - 1) & 0xfff)
142 #define SUN4I_TCON1_BASIC2_X(width)			((((width) - 1) & 0xfff) << 16)
143 #define SUN4I_TCON1_BASIC2_Y(height)			(((height) - 1) & 0xfff)
146 #define SUN4I_TCON1_BASIC3_H_TOTAL(total)		((((total) - 1) & 0x1fff) << 16)
147 #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
151 #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
154 #define SUN4I_TCON1_BASIC5_H_SYNC(width)		((((width) - 1) & 0x3ff) << 16)
155 #define SUN4I_TCON1_BASIC5_V_SYNC(height)		(((height) - 1) & 0x3ff)
186 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space)		((((space) - 1) & 0xfff) << 16)
187 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size)		(((size) - 1) & 0xfff)
190 #define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num)		(((num) - 1) & 0xffff)
216 #define SUN6I_TCON0_LVDS_ANA0_PD(x)			(((x) & 3) << 4)
241 	bool	has_lvds_alt;	/* Does the LVDS clock have a parent other than the TCON clock? */
244 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
245 	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
250 	/* handler for LVDS setup routine */
267 	/* Possible mux for the LVDS clock */